Rabbit 2000, User Manual

Page: 35 / 230

User’s Manual 29
3.3.8 Input/Output Instructions
The Rabbit uses an entirely different scheme for accessing input/output devices. Any
memory access instruction may be prefixed by one of two prefixes, one for internal I/O
space and one for external I/O space. When so prefixed, the memory instruction is turned
into an I/O instruction that accesses that I/O space at the I/O address specified by the 16-
bit memory address used. For example
IOI LD A,(0x85) ; loads A register with contents
; of internal I/O register at location 0x85.
LD IY,0x4000
IOE LD HL,(IY+5) ; get word from external I/O location 0x4005
By using the prefix approach, all the 16-bit memory access instructions are available for
reading and writing I/O locations. The memory mapping is bypassed when I/O operations
are executed.
I/O writes to the internal I/O registers require only two clocks, rather than the minimum of
three clocks required for writes to memory or external I/O devices.
In certain conditions where an I/O operation is followed by a special one-byte instruction,
a bug in the original Rabbit 2000 chip causes an I/O access to take place instead of a mem-
ory access operation. The problem was corrected in revisions A–C of the Rabbit 2000.
(Refer to Appendix B for further information to determine which version of the Rabbit
2000 chip you are using.)
The bug is manifested if an I/O instruction (prefix
IOI
or
IOE
) is followed by one of 12
single-byte op codes that use HL as an index register. The 12 instructions are:
where
r
, an 8-byte register, is one of
A
,
B
,
C
,
D
,
E
,
H
, or
L
.
The only combination that is very likely to occur in user written assembly language pro-
grams is an I/O instruction followed by
LD (HL),r
.
The nature of the failure is that the memory address translation does not take place and so
the appropriate memory chip select will not be enabled for the second instruction. In the
case of external I/O operations where the I/O strobes on Port E may be enabled, an I/O
“chip select” (I/O strobe) will take place instead of a memory chip select. If one of the
above instructions follows an internal I/O operation and the memory access takes place in
the base region where address translation does not take place, the memory operation will
take place properly because the appropriate memory chip select is enabled for internal I/O
operations.
ADC A,(HL)
ADD A, (HL)
AND (HL)
CP (HL)
OR (HL)
SBC A,(HL)
SUB (HL)
XOR (HL)
DEC (HL)
INC (HL)
LD r,(HL)
LD (HL),r