Quin Systems Limited
CPU360 Issue D/E Hardware Manual
Issue 4
June 2004
(MAN530)
Page 1: ...Quin Systems Limited CPU360 Issue D E Hardware Manual Issue 4 June 2004 MAN530 ...
Page 2: ...Quin Systems Limited CPU360 Issue D E Hardware Manual Issue 4 April 2004 MAN530 ...
Page 3: ... described in this document in order to improve design or performance and for further product development Examples given are for illustration only and no responsibility is assumed for their suitability in particular applications Reproduction of any part hereof without the prior written consent of Quin Systems is prohibited Although every attempt has been made to ensure the accuracy of the informat...
Page 4: ...ions Ports 10 2 10 Ethernet Port 10 2 11 Daughter Board Port 11 2 12 Serial Ports 12 2 13 Serial Eeprom 13 2 14 Other Signals 13 2 15 CANbus Ports 13 2 16 Daughter Board 13 3 Configuration 14 3 1 Eprom Flash Pin 31 J1 14 3 2 Eprom Flash Pin 1 J2 14 3 3 Dram Burst Addressing J3 14 3 4 Serial Eeprom Write Protect J4 14 3 5 Interrupt Configuration J5 14 3 6 Reset and Watchdog J6 15 3 7 Processor Conf...
Page 5: ...19 4 3 Serial Ports 19 4 4 CANbus 20 4 5 Daughter Board 21 4 6 Ethernet 21 4 7 G64 Bus 22 4 8 General Purpose I O 23 4 9 Background Debug Port 24 4 10 JTAG Port 24 5 Diagnostics and Tests 25 5 1 Switch on Self Test 25 5 2 Entry to Flashboot Diagnostics 25 5 3 Update Commands 25 5 4 Exit to PTS code 26 5 5 LED functions 26 Index 27 ...
Page 6: ... J7 15 Figure 7 CIO clock frequency J8 16 Figure 8 Serial port A override J9 17 Figure 9 Static ram size J10 17 Figure 10 CANbus interrupts J11 17 Figure 11 Jumper locations 18 Table 12 CPU360 serial port connections 19 Table 13 CANbus connections 20 Table 14 Bitbus connections 21 Table 15 Ethernet AUI connections 21 Table 16 G64 bus connections P1 22 Table 17 General purpose I O connections P2 23...
Page 7: ...d to the Ethernet port one is reserved for use with a protocol specific daughter board and the remaining two are configurable separately for RS 232 or RS 485 operation A Z8536 device provides up to 20 digital input output lines at LSTTL levels and up to three counter timers A calendar clock device with battery backup provides date time information A hardware watchdog timer is also available The Et...
Page 8: ...Software Control The CPU360 board makes extensive use of the programmable features of the 68360 cpu and its system integration module SIM These must be correctly set up by any application or system software when the board starts up A brief description of the various control lines used by the CPU360 is given in the following sections 2 3 Chip Selects The programmable chip select pins are used as fo...
Page 9: ...hown in the following table Figure 1 Address map 0x0 0x07FFFFFF 0x08000000 Eprom max 2M G64 bus 0xFFFFFFFF Dram 1M Unused 0x085FFFFF 0x08600000 0x001FFFFF 0x00200000 0x01FFFFFF 0x02000000 0x030FFFFF 0x03100000 0x02FFFFFF 0x03000000 Sram 128k Eeprom 128k Unused Unused 0x020FFFFF 0x02100000 0x0307FFFF 0x03080000 0x0317FFFF 0x03180000 0xFFFEFFFF 0xFFFF0000 0xFFFF084F 0xFFFF0850 I O 0x06FFFFFF 0x07000...
Page 10: ...low for the optional 68040 cpu This means that G64 bus locations are accessed on alternate words Figure 2 G64 bus address map 0x08000000 0x082FFFFF 0x08300000 0x08FFFFFF 0x085FFFFF 0x08600000 Unused G64 bus VMA 0x084FFFFF 0x08500000 0x080FFFFF 0x08100000 0x083FFFFF 0x08400000 0x081FFFFF 0x08200000 Synchronous 2 MHz G64 bus VPA Synchronous 2 MHz G64 bus VMA Synchronous 1 MHz G64 bus VPA Synchronous...
Page 11: ...accessed on the 32 bit processor bus to allow for the optional 68040 cpu This means that the device registers are accessed on every 4th byte only Figure 3 I O address map 0xFFFF0000 0xFFFF083F 0xFFFF0840 0xFFFFFFFF Unused 82527 CAN controller 0 0xFFFF03FF 0xFFFF0400 0xFFFF084F 0xFFFF0850 0xFFFF07FF 0xFFFF0800 256 bytes 82527 CAN controller 1 256 bytes RTC72423 real time clock 16 bytes Z8536 CIO 4 ...
Page 12: ...programmed for use with the memory configuration used on the CPU360 board by programming the port E pin assignment register PEPAR Set bit 7 to 1 to enable WE0 3 instead of A28 31 Set bit 6 to 1 to enable the AMUX function for dram address multiplexer control Set bits 4 and 2 to 0 to select the CAS0 3 functions for the dram column address strobes For more details on setting up the memory controller...
Page 13: ...rial port A The 68EN360 cpu has some software control over various functions of each port usually by means of programmable output port pins 2 10 Ethernet Port The Ethernet port uses all of the signal lines available to SCC1 PA0 RXD1 PA1 TXD1 PC0 TENA PC4 CLSN PC5 RENA PA8 TCLK1 PA9 RCLK1 The Ethernet transceiver device the 68160 has several programmable functions These are controlled by output lin...
Page 14: ...hese pins depends on the particular hadrware present on the daughter board Standard daughter boards will be made available for specific communications interfaces as required For example a Bitbus interface board provides an isolated RS 485 interface with software control using the mode signals to select between synchronous or self clocked modes and the data rate for self clocked operation The daugh...
Page 15: ...485 point to point enabled or RS 485 multidrop with tristate control When RS 232 mode is selected ports A and B support hardware handshake using the RTS CTS signals and an optional CD carrier detect signal for use with modems Port B SCC3 Mode PB8 PC2 RS 2320 RTS3 RS 4851 tristate control 0 enabled 1 disabled Port A SCC4 Mode PB9 PC3 RS 2320 RTS4 RS 4851 tristate control 0 enabled 1 disabled Port A...
Page 16: ... operates at a bit rate of up to 1Mbit second It complies with theCAN in Automation CiA draft standard DS1 0 2 V ersion2 0 CAN Physical Layer for Industrial Applications The CANbus implementation requires an external power supply to provide power to the isolated transceivers If the CANbus is disconnected or the power supply is not present then the CANbus interface will not operate An optocoupler d...
Page 17: ...3 allows the dram memory to be configured for burst cycles when used with the optional 68040 processor For normal operation with the 68360 processor link pins 1 3 and 2 4 To allow burst cycle operation with the optional 68040 processor link pins 3 5 and 4 6 3 4 Serial Eeprom Write Protect J4 To write protect the serial eeprom device IC16 fit a link to jumper J4 3 5 Interrupt Configuration J5 Jumpe...
Page 18: ...ted to pins 5 6 and 7 8 Figure 5 Reset and watchdog J6 3 7 Processor Configuration J7 Jumper J7 is used to set the processor configuration For normal use with the 68360 cpu link J7 pins 1 2 3 4 and 7 8 For use with the optional 68040 cpu link J7 pins 5 6 only To disable the MMU on a full 68040 cpu link J7 pins 11 and 12 This has no effect on the 68360 cpu or on other variants of the 68040 such as ...
Page 19: ...e clock select line to 0V The table below shows the clock division ratios for all link settings and the peripheral clock speeds fo r a 24MHz main processor clock A B C Divisor 24 MHz in in in 2 12 MHz out in in 4 6 MHz default in out in 8 3 MHz out out in 16 1 5 MHz in in out 32 750 kHz out in out 64 375 kHz in out out 128 187 5 kHz out out out 256 93 75 kHz The clock oscillator enable input pin S...
Page 20: ... the appropriate address line configuration For normal operation with a 128k 8 device e g HM628128 link J10 pins 1 and 2 For use with a 512k 8 device e g HM628512 link pins 2 and 3 Note that the larger static ram is only available if specified when the CPU360 is ordered as the device is in a surface mount package and is soldered directly to the circuit board Figure 9 Static ram size J10 3 11 CANbu...
Page 21: ...anual Copyright 2004 Quin Systems Limited Page 18 3 12 Jumper Locations Figure 11 Jumper locations CPU360 module component side S2 Top Bottom S1 P1 P2 J9 J5 J8 J4 J6 1 1 1 S5 S6 S4 S3 J2 1 J1 1 J3 1 1 J7 1 P3 1 J11 1 P4 1 J1 1 ...
Page 22: ...a 2c 31a 31c 12V P1 pin 30a P2 pin 30a 12V P1 pin 30b P2 pin 30c Where the CPU360 is used as a Machine Manager these supply rails are given by a dedicated backplane taking 24 volts input 4 3 Serial Ports The following table shows the CPU360 serial port connections on the 9 way D sockets in position S4 Port A uses the lower socket and port B uses the upper socket The normal configuration in the PTS...
Page 23: ...nections for the CANbus interfaces on the front panel 9 way plugs and sockets are shown below Note that these comply with the CAN in Automation CiA draft standard DS102 Version 2 0 CAN Physical Layer for Industrial Applications Note that the CANbus interfaces require an external power supply to power the isolated network transceivers This may be connected via any of the normal D type connectors or...
Page 24: ... in position S3 The Bitbus daughter board links the plug and socket together pin to pin to allow daisy chain cable connections Note that the Bitbus interface is fully isolated from the CPU360 power supplies 4 6 Ethernet The CPU360 provides an Ethernet interface using either a standard AUI port or a twisted pair 10baseT interface The AUI port uses a standard 15 way D socket and the twisted pair por...
Page 25: ... DS0 11a Data strobe DS1 11b 12a Bus busy BBUSY 12b SYSCLK 13a E clock 13b Valid peripheral address VPA 14a Reset output RESET 14b MRDY or DTACK 15a Non maskable interrupt NMI 15b Valid memory address VMA 16a Interrupt request IR 16b Read write R W 17a Fast interrupt request FIRQ 17b 18a 18b Data line D8 19a Data line D12 19b Data line D9 20a Data line D13 20b Data line D10 21a Data line D14 21b D...
Page 26: ...t line PC 7c Port line PC3 8a Port line PC 8c 0V 9a 0V 9c Port line PB1 10a Port line PB0 10c Port line PB3 11a Port line PB2 11c Port line PB5 12a Port line PB4 12c Port line PB7 13a Port line PB6 13c Port line PC1 14a Port line PC 14c Port line PC3 15a Port line PC 15c 0V 16a 0V 16c 17a 17c 18a 18c 19a 19c 20a 20c 21a 21c 22a 22c 23a 23c 24a 24c CAN0 V 7 13V 25a CAN0 V 7 13V 25c CAN0 0V 26a CAN0...
Page 27: ... supplied by JTAG Technologies BV It is used during board testing Test methods using access through the JTAG port are described in the Controller Repairs Test Specification document reference TST026 For JTAG testing remember to link J7 9 10 unless the 68040 is fitted Pin no Signal Pin no Signal 1 DS 2 BERR 3 0V 4 BKPT DSCLK 5 0V 6 FREEZE 7 RESET 8 IFETCH DSI 9 5V 10 IPIPE DSO Table 7 Background de...
Page 28: ...TS to the flashboot at the same time as the terminal changes to 38400 baud Or if there is no live PTS the terminal anyway selects 38400 baud From there user selection of Unlock will await a PTS response to the UNLOCK string then act as a terminal in the faster flashboot mode The flashboot Help prompt is given Flash Boot Version 2 2 05 19 00 h boot Restart the processor erase start num Erase num se...
Page 29: ... to PTS code select Restart to run the new PTS firmware just loaded 5 4 Exit to PTS code This uses the b command from the menu Restart on the Toolkit window toolbar will give the b command and change the terminal baud rate back to 9600 5 5 LED functions LEDs are used as follows working from top of the board left nearest board to right Red L4 COM board communications error Green L3 A COM board Read...
Page 30: ...rial port 19 D daughter board 13 connections 21 daughter board port 11 diagnostic LEDs 13 download firmware 26 dram burst addressing 14 E eprom flash pin 1 14 eprom flash pin 31 14 Ethernet connections 21 Ethernet port 10 Ethernet transceiver 10 F firmware upgrade upgrade 26 flashboot 25 force RS 232 on port A 17 G G64 bus address map 7 connections 22 general purpose I O connection 23 H hardware w...
Page 31: ...iguration 15 RS 232 12 RS 485 12 S self test 25 serial eeprom 13 serial eeprom write protect 14 serial port A override 17 serial port connections 19 serial port 12 signal names 19 SIM module 9 static ram size 17 switch locations 18 T tristate control 12 twisted pair 10 W watchdog configuration 15 write protect serial eeprom 14 ...
