5G Module Series
RM505Q-AE Hardware Design
RM505Q-AE_Hardware_Design 40 / 79
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
PCM_DIN
125
μ
s
MSB
1
2
32
31
LSB
Figure 22: Auxiliary Mode Timing
The following table shows the pin definition of PCM interface which can be applied to audio codec design.
Table 12: Pin Definition of PCM Interface
The clock and mode can be configured by AT command, and the default configuration is master mode
using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See
document [2]
for details about
AT+QDAI
command.
“*” means under development.
Pin No. Pin Name
I/O
Description
Comment
20
PCM_CLK
IO
PCM data bit clock
1.8 V power domain
In master mode, it is an output signal.
In slave mode, it is an input signal.
If unused, keep it open.
22
PCM_DIN
DI
PCM data input
1.8 V power domain
24
PCM_DOUT
DO
PCM data output
1.8 V power domain
28
PCM_SYNC
IO
PCM data frame sync
1.8 V power domain
NOTE