5G Module Series
RM502Q-GL Hardware Design
RM502Q-GL_Hardware_Design 35 / 77
3.8. PCIe Interface
RM502Q-GL provides one integrated PCIe (Peripheral Component Interconnect Express) interface which
complies with the
PCI Express Base Specification, Revision 3.0
and supports up to 8 Gbps per lane.
⚫
PCI Express Base Specification Revision 3.0 compliance
⚫
Data rate up to 8 Gbps per lane
The following table shows the pin definition of PCIe interface.
Table 10: Pin Definition of PCIe Interface
3.8.1. Endpoint Mode
RM502Q-GL supports endpoint (EP) mode. In this mode, the module is configured as a PCIe EP device.
The following figure shows a reference circuit of PCIe EP mode.
Pin No. Pin Name
I/O
Description
Comment
55
PCIE_REFCLK_P
AI/AO
PCIe reference clock (+)
100 MHz. Require differential
impedance of 85
Ω
53
PCIE_REFCLK_M
AI/AO
PCIe reference clock (-)
49
PCIE_RX_P
AI
PCIe receive data (+)
Require differential impedance
of 85
Ω
47
PCIE_RX_M
AI
PCIe receive data (-)
43
PCIE_TX_P
AO
PCIe transmit data (+)
Require differential impedance
of 85
Ω
41
PCIE_TX_M
AO
PCIe transmit data (-)
50
PCIE_RST_N
DI
PCIe reset.
Active LOW.
Open drain
52
PCIE_CLKREQ_N
DO
PCIe clock request.
Active LOW.
Open drain
54
PCIE_WAKE_N
DO
PCIe PME wake.
Active LOW.
Open drain
