LTE-A Module Series
EG18 Hardware Design
EG18_Hardware_Design 61 / 104
In addition, RI behavior can be configured flexibly. The default behavior of the RI is shown as below.
Table 24: RI Behaviors
The RI behavior can be changed by executing
AT+QCFG="urc/ri/ring"
command. Please refer to
document [3]
for more details.
3.17. PCIe Interface*
EG18 provides one integrated PCIe (Peripheral Component Interconnect Express) interface which
complies with the PCI Express Specification, Revision 2.1 and supports 5Gbps per lane. The PCIe
interface of EG18 is only used for data transmission.
PCI Express Specification Revision 2.1 compliance
Data rate at 5Gbps per lane
Can be used to connect to an external Ethernet IC (MAC and PHY) or WLAN IC
The following table shows the pin definition of PCIe interface.
Table 25: Pin Definition of the PCIe Interface
State
Response
Idle
RI keeps at high level
URC
RI outputs 120ms low pulse when a new URC returns
Pin Name
Pin No.
I/O
Description
Comment
PCIE_REFCLK_P
179
AI/AO
Input/Output PCIe
reference clock (+)
If unused, keep it open.
PCIE_REFCLK_M
180
AI/AO
Input/Output PCIe
reference clock (-)
If unused, keep it open.
PCIE_TX_M
182
AO
PCIe transmit (-)
If unused, keep it open.
PCIE_TX_P
183
AO
PCIe transmit (+)
If unused, keep it open.
PCIE_RX_M
185
AI
PCIe receive (-)
If unused, keep it open.
PCIE_RX_P
186
AI
PCIe receive (+)
If unused, keep it open.
