LTE-A Module Series
EG06 Hardware Design
EG06_Hardware_Design 47 / 89
Table 12: Pin Definition of the Debug UART Interface
Table 13: Pin Definition of the BT UART Interface
The logic levels are described in the following table.
Table 14: Logic Levels of Digital I/O
DCD
59
DO
Data carrier detection
1.8V power domain
CTS
56
DO
Clear to send
1.8V power domain
RTS
57
DI
Request to send
1.8V power domain
DTR
62
DI
Data terminal ready,
Sleep mode control
1.8V power domain
TXD
60
DO
Transmit data
1.8V power domain
RXD
58
DI
Receive data
1.8V power domain
Pin Name
Pin No.
I/O
Description
Comment
DBG_TXD
137
DO
Transmit data
1.8V power domain
DBG_RXD
136
DI
Receive data
1.8V power domain
Pin Name
Pin No.
I/O
Description
Comment
BT_TXD
163
DO
Transmit data
1.8V power domain
BT_RXD
165
DI
Receive data
1.8V power domain
BT_CTS
164
DO
Clear to send
1.8V power domain
BT_RTS
166
DI
Request to send
1.8V power domain
Parameter
Min.
Max.
Unit
V
IL
-0.3
0.6
V
V
IH
1.2
2.0
V
V
OL
0
0.45
V
