LPWA Module Series
BG77 Hardware Design
BG77_Hardware_Design 24 / 76
1. PWRKEY output voltage is 1.5V because of the voltage drop inside the Qualcomm chipset. Due to
platform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, PWRKEY
should never be pulled down to GND permanently.
2. RESET_N is multiplexed from PWRKEY.
3. The input voltage range of USB_VBUS is 1.3V ~ 1.8V.
4. USB_VDDA_3P3 and EXT_PWR_EN pins are used for USB PHY circuits.
5. W_DISABEL#, AP_READY, USIM_DET, PCM, I2C, GRFC and GPIO functions are under
development.
6. SPI_MOSI(pin40), NETLIGHT(pin79) and GPRC1(pin83) are BOOT_CONFIG pins, They should not
be pulled up before startup.
7. ADC input voltage must not exceed 1.8V.
8. Keep all RESERVED pins and unused pins unconnected.
9. “*” means under development.
3.3. Operating Modes
The table below briefly summarizes the various operating modes of BG77.
interface before
startup
1.8V power domain.
If unused, keep this
pin open.
GRFC2 94
DO
General RF
control
interface
V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
If unused, keep this
pin open.
RESERVED Pins
Pin Name
Pin
No.
I/O
Description
DC Characteristics Comment
RESERVED
29,
48~51,
59,
67~71,
80~82,
91~93
Reserved
Keep these pins
open.
NOTES
