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Coherent Modulation Transmitter | IQTX
Quantifi Photonics Ltd.
Version
1.04
46
Message queues
Information is exchanged in the form of messages. These messages are held in input and output queues.
The output queue stores responses to query commands. The CohesionSCPI service transmits any data
in the output queue when a read request is received. Unless specified in the command description, all
output response data is transmitted in ASCII format.
Status and event registers
11.2.1
Standard Event Status Register
The Standard Event Status Register (SESR) is modified by the IQTX with the results of the command
operations.
Bit
Description
7 (MSB), 6
Not used
5
Is set when a Command Error event has been detected
4
Is set when a command Execution Error has been detected
3
Is set when a Device Dependent Error event has been detected
2
Is set when there a Query Error event has been detected
1
Not used
0 (LSB)
Is set when an Operation Complete event has been generated
11.2.2
Standard Event Status Enable Register (Mask)
The Standard Event Status Enable Register (SESR Mask) is used to build the Event Status Bit (ESB)
within the Status Byte Register (STB). To ignore any of the events detected and set in the SESR, set the
corresponding bit within the SESR Mask to 0. The STB can then be queried and the value of the ESB can
be used to determine service request requirements based on the SESR Mask applied.
The default bit values within the SESR Mask are all 0.
11.2.3
Status Byte Register
The Status Byte Register (STB) is built from all other status registers and masks. This register can be
used in queries to determine if an event has been detected and where that event has been detected.
Bit
Description
7 (MSB)
Not used
6
The Master Summary Status (MSS) bit is set from the STB and SRE Mask
5
The Event Status Bit (ESB) is set from the SESR and the SESR Mask
4
Message Available (MAV) is set when there is data in the output queue
3, 2, 1, 0 (LSB)
Not used
11.2.4
Service Request Enable Register (Mask)
The Standard Request Enable Register (SRE Mask) is used to build the Master Summary Status Bit
(MSS) within the Status Byte Register (STB). To ignore any of the events detected and set in the STB
register itself, set the corresponding bit within the SRE Mask to 0. The STB can then be queried and the
value of the MSS can be used to determine the type of service request required based on the SRE Mask
applied.
The default bit values within the SESR Mask are all 0.