3.6
Interface configuration
The configuration of the 6-pin interface (and indeed, the 4-pin interface on the right edge of
the board) is controlled by the jumper wire area above the 6-pin interface pin header pads.
In the default configuration (specified by the tinned copper traces jumper wires), all outputs
are 5V logic level
In the following description, the nomenclature adopted is – as illustrated in the diagram
(right):
UPPER: means the jumper wire is connected from the center of the group of three pads, to
the top pad.
LOWER: means the jumper wire is connected
from the center of the group of three pads, to
the lower pad.
1. PPS voltage level:
UPPER: 5V logic level (DEFAULT)
LOWER: 2.8V logic level
2. TxD voltage level
(GNSS module serial data output, which is the TxD pin on the 4-pin
header at the right of the board):
UPPER: 5V logic level (DEFAULT)
LOWER: 2.8V logic level
4. Circuit diagram (schematic) and description
In the above circuit below, the position of the default jumper wires, which are implemented
by tinned copper traces on the PCB underside, are indicated with a thick red line.
QLG2-SE manual 1.00
9
