Power Application Controller
®
-113-
Copyright 2020 © Qorvo, Inc.
Rev 1.0
– Jan 17, 2020
10.9 Cycle by Cycle Current Limit
To provide hardware assist for current limit, the ASPD may be configured to temporarily disable
the gate drivers, when the current is over a configured threshold. This method is duty cycle
truncation and is most useful in edge-aligned PWM topologies, for 120-degree commutation.
During these events, the ASPD may turn off all the high-side, low-side or high-side and low-side
gate drivers based on the state of the Signal Manager HPCOMP/LPCOMP comparators. This
can allow applications to have cycle by cycle current limit, without intervention of the MCU.
The diagram below shows how the protection comparators can be used to generate an event
signal PWMCBC, which can be used to control this operation.
Figure 10-4
Cycle by Cycle Current Limit
The mask signal (
CFGDRV2.nDRVxyDISM
) is used to select which half-bridge to enable cycle-
by-cycle current limit on, while
CFGDRV2.LPCBCHS
and
CFGDRV2.LPCBCLS
are used to
select the high-side or low-side gate driver for the half-bridge to disable.
The real-time status of which half-bridge is in cycle-by-cycle current limit operation is available
in
STATDRV.DRVxyDISSTAT
. The latched status is available in
STATDRV.DRVxyDIS
.
During operation, if the PWMCBC signal is high, then the output to the configured gate drivers is
temporarily disabled, until the PWMCBC becomes available again. The following shows which
drivers are disabled during this condition:
