Qorvo PAC25140, User Manual

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PAC25140 Users Guide Preview
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Rev. 1.0.0 28 February 2023 © 2023 Qorvo US, Inc.
49 of 77
SOC.AIO0CFG
Register 8-10
. SOC.AIO0CFG (Analog I/O 0 Configuration, SOC 0x09)
BIT NAME ACCESS RESET DESCRIPTION
7:4 MUXSEL R/W 0x0
AIO0 Mux Select -
during I/O output
mode
0: ADC VREF = 2.5V
1: AFEMUXOUT
2: IMUXOUT
3: VBMUXOUT
15:4: RFU
4 RFU R/W 0x0 Reserved
3:2 SWAP R/W 0x0
Swaps the offset of
the buffer.
0: No swap
1: Swap
1 MODE R/W 0x0
AIO0 Buffer Mode
0: Input Buffer Mode
1: Output Buffer mode
(2mA drive strength)
0 AIO0EN R/W 0x0
AIO0 Buffer Enable
0: Disabled
1: Enabled
SOC.PROT_KEY
Register 8-11
. SOC.PROT_KEY (Protection Key, SOC 0x10)
BIT NAME ACCESS RESET DESCRIPTION
7:0 KEY RW 0
Protection Key
Select SOC registers
require that
PROT_KEY..KEY be
written with 0xA5
before those registers
can be written. The
KEY field is self
clearing to 0x0 after
any write to one of the
select registers.