QMTECH XC7A 100T Starter Kit
User Manual V01
2.2.3
System Clock
FPGA chip XC7A100T-2FTG676I has system clock frequency 50MHz which is directly provided by external
crystal. The crystal is designed with high accuracy and stability with low temperature drift 10ppm/
°
c. Below
image shows the detailed hardware design:
Figure 2-9. 50MHz System Clock
2.2.4
User Extension IOs
The core board has two 64P 2.54mm pitch f emale headers which are used f or extending user modules,
such as ADC/DAC module, audio/video module, ethernet module, etc.
C2
100NF
50 MHz
VDD
VSS
OUT
OE
Y 1
SG-8002JC-50.0000M-PCB
4
1
3
2
SY S_CLK
R13
4.7K
3V3
IO_N2
IO_N3
IO_A2
IO_A3
IO_B4
IO_A5
IO_A4
IO_B5
IO_H4
IO_J4
IO_G2
IO_G1
IO_D1
IO_E1
IO_F4
IO_G4
U2
HDR_32X2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VCCO_34_35
IO_C1
IO_B1
IO_E2
IO_F2
VCCO_34_35
IO_H2
IO_H1
IO_M2
IO_L2
VIN_5V
VIN_5V
IO_B2_VREF
IO_C2
IO_U2
IO_U1
IO_D5
IO_E5
IO_D4
IO_C4
IO_H9
IO_G9_VREF
IO_T2
IO_R2
IO_R1
IO_P1
IO_N1
IO_M1
IO_P5_VREF
IO_P6
IO_K1
IO_J1
IO_T4
IO_T3
IO_M6
IO_M5_VREF
IO_L5
IO_M4
IO_L4
IO_P3
IO_R3
IO_K5
BANK34/35 Volta ge
Supply Pins.
Connected to VIN
power hea der.
