Operation
Atlas
®
Digital Amplifier Complete Technical Reference
55
4
4.7
Status Registers
In addition to various numerical registers that may be queried by the external controller, there are five bit-oriented
status registers.
These status registers conveniently combine a number of separate bit-oriented fields into a single register. These
registers are Event Status, Drive Status, Signal Status, SPI Status, and Drive Fault Status Register. The external
controller may directly query these four registers, or the contents of these registers may be utilized by other functional
portions of Atlas, such as
FaultOut
signal processing. See
Section 4.8.8, “FaultOut Signal”
for more information on
FaultOut
processing.
4.7.1
Event Status Register
The Event Status register is defined in the following table:
The command
GetEventStatus
returns the contents of the Event Status register.
Bits in the Event Status register are latched. Once set, they remain set until cleared by an external controller instruction
or a reset. Event Status register bits may be reset to 0 by the instruction
ResetEventStatus
, using a 16-bit mask.
Register bits corresponding to 0s in the mask are reset; all other bits are unaffected.
4.7.2
Drive Status Register
The Drive Status register is different than the Event Status register in that the contents are not latched, but rather
continuously set and reset by Atlas to indicate the status of the corresponding conditions.
The specific status bits provided by the Drive Status register are defined in the following table:
Bit
Name
Description
0-6
Reserved
May contain 0 or 1.
7
Instruction error
Set when an instruction error occurs. This may be due to an incorrect command
transmission, an Atlas-detected checksum error, or various other SPI interface
command-related conditions.
8
Reserved
May contain 0 or 1.
9
Overtemperature fault
Set when an overtemperature fault occurs.
10
Drive exception
Set when a drive exception event such as bus voltage fault, watchdog timer fault,
overcurrent fault, or deassertion of the enable pin occurs that causes Atlas to dis-
able output.
11
Reserved
May contain 0 or 1.
12
Current foldback
Set when current foldback occurs.
13-15
Reserved
May contain 0 or 1.
Bit
Name
Description
0
Reserved
May contain 0 or 1.
1
In foldback
Set 1 when in foldback, cleared 0 if not in foldback.
2
Overtemperature
Set 1 when currently in an overtemperature condition. Cleared 0 if currently not
in an overtemperature condition.
3
Reserved
May contain 0 or 1.
4
In holding
Set 1 when in a holding current condition. Cleared 0 if not in a holding current
condition.
5
Overvoltage
Set 1 when currently in an overvoltage condition. Cleared 0 if currently not in an
overvoltage condition.
