SH-D09
16
A
B
C
D
1
2
4
1
2
4
3. BLOCK DIAGRAM AND SCHEMATIC DIAGRAM
3.1 BLOCK DIAGRAM
TUNER
VSB
DECODE
RF
SW
ST20 TP4
TS DECODE
R/C MICON
FPGA
RESET
CONFIG
AD DECODE
Flash
4M Byt
(8Mbit x 4)
DRAM
4M Byt
(16Mbit x 2)
VCXO
27M
TSIN
JTAG
AIR
CABLE
DIGITAL
EXPANSION
PORT
EEP
ROM
(8k bit)
IIC-2
IIC-1
VCXO
10.7M
UART
MDA 8b
MAD 8b, R/W
nREQ,nSTRB
IRQ,nCS
CLK
IN+/-
TSD 8b
TSVAL,CLK
LOCK,ERROR
EQ,PSYNC
nCS 2b
MDA 32b
MAD 19b
nRST,nWE
MDA 32b
MAD 10b
nRST
RST
PWM
MODE 4b
CLK ,DONE
nCON,nSTATUS,DATA
TDO,TDI
TCK,TMS
JnRST,JnREST
ST20ERR
IIC-3
JnRSET
MREQ
INT
BUSY
TXD
RXD
BUG
FIX
(25Pin
D-sub)
IC5216
P5201
IC5201
IC5211-3
SW
IC5207-8
IC5203-6
IC5101
X5202
IC5002
X5001
P5003
P5221
IC5217
IC5202
SC5201
SC5202
MDA 4b
MAD 4b
nMOE,
nCS 2b
nMCSROM
nMRAS2
nWDRST
RFSW
UNIT5002
TU5001
MODE-SW
S5101
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TEL 13942296513
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