Pioneer CDJ-850, Service Manual

Page: 31 / 122

31
CDJ- 8 50
5 6 7 8
5 6 7 8
A
B
C
D
E
F
10.14
WA
V EFORMS
[10] Confirmation of basic operations of the CPU/DSP
First, check if the voltage at each section is OK.
[10-1] Periphery of the MAIN CPU: IC103
1
MAI N Assy
MAI N _CPU
(IC103)
Check the waveforms and levels of the following
signals:
• MAI
N _XRST: MAI N CPU releases reset with "H".
• 33 MHz OSC circuit: Oscillation circuit for
system clock.
• 48 MHz OSC circuit: Oscillation circuit for USB
clock.
• SH_STATUS: Status signal of MAI
N CPU.
"H/L" pulse signal in the normal state.
• CLK66M: 66 MHz clock signal output for FLASH
ROM and SDRAM.
If both the Reset and Oscillation circuits are OK, but the
SH_STATUS signal is fixed at "L" or "H" (not "H/L" pulse
signal), the Main CPU is not operating.
If the reset is not "H", following points may be defective.
• Loose connection of the reset line
• Defective part of PA
N EL CPU(IC1007)
• Malfunction detection of the voltage.
If both the Reset, Oscillation circuits and 66 MHz clock
signals are OK, IC103 (MAI
N CPU), IC101 (FLASH ROM)
or IC102 (SDRAM) may be defective.
—
10.14
WA
V EFORMS
[10-2] SERVO DSP: IC201
1
MAI N Assy
SER V O DSP
(IC201)
Check the waveforms and levels of the
following signals (in CD PLAY mode):
• SR
V RST: SER V O DSP releases reset with "H".
• CLK_S_16M: 16 MHz system clock signal input.
• SR
V SCLK: Communication clock signal.
If both the Reset and System clock signals are OK,
but the SR
V SCLK signal is not output, the SER V O
DSP (IC201) may be defective.
—
10.14
WA
V EFORMS
[10-3] AUDIO DSP: IC301
1
MAI N Assy
AUDIO DSP
(IC301)
Check the waveforms and levels of the
following signals (in PLAY mode):
• DSPDREQ: Communication request signal
• DSPRST: AUDIO DSP releases reset with "H".
• CLK_A_16M: 16 MHz system clock signal input.
If both the Reset and System clock signals are OK,
but the DSPDREQ signal is not output, the AUDIO
DSP (IC301) may be defective.
—
10.14
WA
V EFORMS
[10-4] PANEL CPU: IC1007
1
DFLB Assy
PA N EL CPU
(IC1007)
Check the waveforms and levels of the following
signals:
• RESET(IC1007-pin 12): PA
N EL CPU releases
reset with "H".
• 16 MHz OSC circuit: Oscillation circuit for
system clock.
• TSCK(IC1007-pin 37): Communication clock
signal output. If both the Reset and Oscillation circuits are OK, but
the TSCK signal is not output, the PA
N EL CPU
(IC1007) may be defective.
—
No. Cause Diagnostics Point Item to be Checked Corrective Action Reference
No. Cause Diagnostics Point Item to be Checked Corrective Action Reference
No. Cause Diagnostics Point Item to be Checked Corrective Action Reference
No. Cause Diagnostics Point Item to be Checked Corrective Action Reference
P
4 1
R
3 6
Q
5 2
G
8
10.15 EACH
SIG
N AL LE V EL
10.15 EACH
SIG
N AL LE V EL
10.15 EACH
SIG
N AL LE V EL
10.15 EACH
SIG
N AL LE V EL