Phytec phyCORE-PXA270, Hardware Manual

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Carrier Board phyCORE-PXA270
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PHYTEC Meßtechnik GmbH 2006 L-668e_1
The PXA270 PCMCIA interface does not support TrueIDE mode.
When operating in TrueIDE mode signals /IDE_PCE1 and
/IDE_PCE2 don't control the LowByte and HighByte but two different
memory areas. LowByte or HighByte are selected via address line A0
in TrueIDE mode. PLD U6 allows access to the two separate memory
areas (control register 1 - bit 0 = 1) by using address line A11 in order
to decide which of the two Chip Select signals is active.
A11 /IDE_PCE1 and /IDE_PCE2 Level
0 /IDE_PCE1 = active, /IDE_PCE2 = not active
1 /IDE_PCE2 = active, /IDE_PCE1 = not active
Table 25: TrueIDE Memory Area Assignment
Based on the above assignment scheme the following memory areas
are used in conjunction with the physical address range of the
PXA270 controller. It should be noted that operating systems, such as
Linux and WinCE, use virtual addresses. This means that physical
addresses can also be mapped to other memory areas.
Active Address Range Corresponding Chip Select Signal
0x2000 0000 /IDE_PCE1
0x2000 0800 /IDE_PCE2
Table 26: Physical Address Range of the IDE Interface
For more information refer to the applicable IDE data sheet.