Phytec phyCORE-PXA270, Hardware Manual

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Memory Configuration
J15
J27
J3
U12
D7
U13
R60
U2
U22
U21
XT2
U10
J10
PXA270
XT1
U3
L1
J23
R103
J9
J21
Q6
J6
J32
X2
D6
Q1
U7
J30
R13
J16 J17
J29
U5
XT4
J26
U15
J11
U20
J2
J28
J19
J20
xData
xAdress
PCTRL
U6
D0-15
A0-25
IDE
Connector
Figure 16: IDE Circuitry
The PCMCIA interface settings are made in the PXA270 controller.
The IDE registers within PLD U6 along with their reset values are
given in the following table.
REG ADDR D7 D3 D2 D1 D0
IDE 0
0x20001000 Res Res PM_5V RES RES
Reset 0 X 0 0
IDE 1
0x20001002 Res DMA0/1 DMAEN RES IDE/MEM
Reset 0 0 0 1
IDE 2
0x20001004 Res RDY Res IDE_RES RES
Reset 0 0 0 1
IDE 3 0x20001006 Res Res IDEIN IDEON IDEOE
Reset 0 0 0 0
IDE 4 0x20001008 Res IDE5V RES 5V/3V IDEPWR
Reset x 0 1 0
Table 19: IDE Control Register with Reset Values
The operating states of the 5 V supply voltage can be read in the IDE
control register 0. If the Carrier Board's input voltage drops below
8 V, the 5 V supply voltage will be shut off.
REG ADDR D7 D3 D2 D1 D0
IDE 0 0x20001000 Res Res PM_5V RES RES
RW R/W=0 R/W=0 R R/W=0 R/W=0
Signal
Name PM_5V
Table 20: IDE Control Register 0
PM_5V Reading a "1" from this bit indicates that the 5 V
system supply voltage as well as the LCD voltatge
are active.
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PHYTEC Meßtechnik GmbH 2006 L-668e_1
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