Phytec phyCORE-PXA270, Hardware Manual

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Carrier Board phyCORE-PXA270
22
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PHYTEC Meßtechnik GmbH 2006 L-668e_1
5.2.1 Control PLD (U7) Registers
Control PLD U7 is addressed over the PXA270's Chip Select signal
/CS_1 The bus width is set to 16-bit as a VLIO interface. The registers
of the Control PLD are listed in the following table. The register's
reset value after the system start is shown below the description.
REG ADDR. D7-D4 D3 D2 D1 D0
CTRL0 0x04000000 Res Res GPIO0 RESOUT SRES
RESET 0 0 0
CTRL 1 0x04000002 Res PM_5V CANPWR Res Res
RESET 1 0 0 0
CTRL 2
0x04000004 Res Res LEDUSER LEDBUSY LEDRUN
RESET 0 0 0 0
CTRL 3
0x04000006 Res POS1 POS2 LCDON LCDPWR
RESET 0 0 0 0
CTRL 4
0x04000008 Res Res Res Res MMC1PWR
RESET 0 0 0 0
CTRL 5 0x0400000A Res WP DET LED MMC2PWR
RESET 0 X 0 0
CTRL 6 0x0400000C Res INT3 INT2 INT1 INT0
RESET 0 0 0 0
CTRL 7
0x0400000E Res INT
PM_5V INT
MMCDET INT
FF_RI INT
BT_DET
RESET 0 0 0 0
CTRL 8 0x04000010 Res BT_Rx FF_RI BT_SD FF_SD
RESET 0 0
CTRL 9 0x04000012 Res Res AC97 ENA /FL_DIS FL_WP
RESET 0 0 0 1
CTRL 10
0x04000014 Res GPS_ENA GPS_PWR Res Res
RESET 0 0 0 0
CTRL 11
0x04000016 Res ALARM ACPRES ACSEL ACENA
RESET 0 X 1 1
Table 7: Control PLD U7 Overview and Reset Values