Memory
Configuration
5.2
Control PLD (U7)
Control PLD U7 controls the drivers for the buffered data and the
address bus. Furthermore, all power management, control and
interrupt functions, except for the CF card and the IDE interface, are
integrated in this device. The individual functions will be explained in
greater detail in the register description.
J15
J27
J3
U12
D7
U13
R60
U2
U22
U21
XT2
U10
J10
PXA270
XT1
U3
L1
J23
R103
J9
J21
Q6
J6
J32
X2
D6
Q1
U7
J30
R13
J16
J17
J29
U5
XT4
J26
U15
J11
U20
J2
J28
J19
J20
Data
Adess
Ctrl
Power
X-Bus
LEDs
Detect
Control
U7
Adress-
Decoder
/CS1
Figure 12: Control PLD U7
©
PHYTEC Meßtechnik GmbH 2006 L-668e_1
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Summary of Contents for phyCORE-PXA270
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