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Development Board for phyCORE-PXA255



PHYTEC Meßtechnik GmbH 2004 L-657e_0

The Ethernet chip’s physical memory area is given in the following
table. The address decoder generates the Ethernet /CS at address
0x14000000. In addition an offset of 0x00000300 has to be added.

Ethernet

Start Address

/ OFFSET

0x 1400 0000 + 0x 0000 0300 = 0x 1400 0300

Table 34:

Address Space for Ethernet Controller

Summary of Contents for phyCORE-PXA255

Page 1: ...A product of a PHYTEC Technology Holding company Development Board for phyCORE PXA255 Hardware Manual PCB 1220 1 and 1220 2 Edition November 2004...

Page 2: ...PHYTEC Me technik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Me technik GmbH further re...

Page 3: ...Interface 31 5 3 2 Compact Flash Interface 36 6 Ethernet Interface 41 7 USB Host 43 8 USB Client 45 9 LCD Interface 47 10 RS 232 Interface 49 10 1 FF UART 51 10 2 BT UART 52 10 3 IR UART 53 11 CAN Int...

Page 4: ...Diagram 16 Figure 10 Battery Charger Circuitry 17 Figure 11 Control PLD U6 21 Figure 12 Decoupling the Data and Address Bus 29 Figure 13 CF Card and IDE PLD U7 30 Figure 14 IDE Hard Drive Mounting Loc...

Page 5: ...n Bus Numbering Scheme 69 Figure 40 Physical Dimensions Development Board 87 Figure 41 Physical Dimensions Expansion Board 88 Figure 42 Component Placement Diagram Development Board PCB Revision 1220...

Page 6: ...gister 4 34 Table 24 TrueIDE Memory Area Assignment 35 Table 25 Physical Address Range of the IDE Interface 35 Table 26 CF Card Control Register with Reset Values 37 Table 27 CF Card Control Register...

Page 7: ...rvision with WM9712L 59 Table 43 Sound Jacks 59 Table 44 Expansion Board Connector X30 Pinout 62 Table 45 Expansion Board Connector X31 Pinout 63 Table 46 GPIO Expansion Bus X17 Pin Assignment 77 Tabl...

Page 8: ...Development Board for phyCORE PXA255 PHYTEC Me technik GmbH 2004 L 657e_0...

Page 9: ...nts a logic one or high level signal Declaration regarding Electro Magnetic Conformity of the phyCORE PXA255 Development Board PHYTEC Development Boards henceforth products are designed for installati...

Page 10: ...tic Directives Users should ensure conformance following any modifications to the products as well as implementation of the products into target systems The phyCORE PXA255 Development Board is one of...

Page 11: ...transformer and connector DB 9 USB and power socket connectors The phyCORE module can be plugged like a big chip onto the Development Board s mating Molex connectors Once programmed the phyCORE module...

Page 12: ...rmer for 100 10 MBit s USB host interface circuitry supporting the USB OTG controller on the phyCORE PXA255 USB client socket for PXA255 USB client interface Power supply for unregulated input voltage...

Page 13: ...Introduction PHYTEC Me technik GmbH 2004 L 657e_0 5 PXA255 Operating Systems Kits Linux WinCE phyCORE PXA255 Debugging Systems iSYSTEM iC3000 Active EmulatorTM...

Page 14: ...0 5V TFT LCD 640 480 LCD RGB Pixel Frame Line Enable U48 WM9712L AC97 X26 X28 Line IN OUT MIC Touch Audio X21 2 USB Host 2 USB X22 USB Client PXA255 USB Client U45 Opto P3 CAN CAN SPI P1 P2 2 RS232 FF...

Page 15: ...Interface JTAG Interface Matrix Keyboard AC97 Connector Reset Button GPIO Button MIC IN OUT AC97 AC97 AC97 Expansion Board on Development Board CAN Expansion Connector Figure 2 Development Board Overv...

Page 16: ...ctFlash Card D5 D4 D2 D1 Reset Botton GPIO Botton USB OTG X3 Connector to Base Board X4 Connector to Base Board D3 SOUND Figure 4 Expansion Board Overview Top View USB OTG MultiMedia Card CompactFlash...

Page 17: ...table below Port I O Configuration GPIO0 I GPIO0 as interrupt for RTC GPIO1 I GPIO1 as interrupt wake up for push botton S1 GPIO2 I GPIO2 as Ethernet interrupt GPIO3 I GPIO3 as interrupt 1 for ISP136...

Page 18: ...tCLK GPIO29 I AC97 SDATA_IN0 GPIO30 O AC97 SDATA_OUT GPIO31 O AC97 SYNC GPIO32 I AC97 SDATA_IN1 GPIO33 O CS5 32 bit VLIO for Ethernet controller GPIO34 I FF UART RxD GPIO35 I FF UART CTS GPIO36 I FF U...

Page 19: ...CD GPIO67 O LDD9 data bus for LCD GPIO68 O LDD10 data bus for LCD GPIO69 O LDD11 data bus for LCD GPIO70 O LDD12 data bus for LCD GPIO71 O LDD13 data bus for LCD GPIO72 O LDD14 data bus for LCD GPIO73...

Page 20: ...Development Board for phyCORE PXA255 12 PHYTEC Me technik GmbH 2004 L 657e_0...

Page 21: ...most of which have been installed prior to delivery depending on the board s configuration Solder jumpers should not be changed by the user Figure 6 illustrates the numbering of the jumper pads while...

Page 22: ...escription of the jumper functions is provided in the following manual sections The jumpers are grouped by function as follows Jumper Function Section JP3 JP5 JP6 JP9 USB host Interface refer to secti...

Page 23: ...Card on the Expansion Board can be switched with the help of transistors The voltage converter allows for a maximum current draw of 2 amps at 3 3 V 5 The efficiency of the converter is over 80 Supply...

Page 24: ...e s 3 3 V V C C 3 3 V M M C 2 U S B C F C a r d L C D I n v e r t e r 1 2 V 1 2 V 5 V 5 V I D E P X A 2 5 5 P o w e r L a t c h I D E _ E n a b l e M M C _ E n a b l e C F _ E n a b l e L C D _ E n a...

Page 25: ...put voltage NiMH batteries In this case the BQ24703 battery charge controller switches the voltage from the power adapter to battery operation It will charge the batteries when the Development Board i...

Page 26: ...Development Board for phyCORE PXA255 18 PHYTEC Me technik GmbH 2004 L 657e_0...

Page 27: ...h memory 8 MByte asynchronous CS1 free pre configured 16 bit asynchronous ROM RAM CS2 16 bit VLIO interface expansion connector X17 on the Development Board CS3 16 bit VLIO interface address decoder U...

Page 28: ...ive interrupt for MCP2515 CAN controller GPIO27 EGPIO27 Low active interrupt for MAX7301 matrix keyboard Table 4 Interrupt Assignment phyCORE PXA255 On the Development Board interrupts are used for th...

Page 29: ...r r u p t s P o w e r X B U S L E D s D e t e c t C S 2 C o n t r o l F l a s h 3 2 b i t D 0 D 1 5 V C C _ C O R E U 1 0 D 0 D 1 5 U 1 3 S D R A M B a n k 0 D 1 6 D 3 1 U 1 5 S D R A M B a n k 0 F l...

Page 30: ...C97 ENA FL_DIS FL_WP RESET 0 0 1 CTRL 10 0x0c000014 Res Res Res Res Res RESET CTRL 11 0x0c000016 Res ALARM ACPRES ACSEL ACENA RESET 0 0 Table 6 Control PLD U6 Reset Values The reset properties for RES...

Page 31: ...W 0 R W Table 8 PLD U6 Control Register 1 5V_OFF Turns off the 5 V supply bit set CANPWR Turns on the external CAN supply voltage bit set PM_5V Indicates that 5 V supply voltage is active The registe...

Page 32: ...egister 3 POS1 POS2 The display adjustment is set here The display can be mirrored in the X direction as well as the Y direction with these two bits If both bits are changed at the same time then the...

Page 33: ...g this bit returns a 0 otherwise it is set to 1 Control registers 6 and 7 contain the interrupt sources for the interrupt input GPIO_7 In control register 6 the register bits are deleted by an interru...

Page 34: ...ter 8 controls the RS 232 transceiver for the BT IR UART and the FF UART REG ADDR D7 D4 D3 D2 D1 D0 CTRL 8 0x0c000010 Res BT_Rx FF_RI BT_SD FF_SD RW R W 0 R R R W R W Table 14 PLD U6 Control Register...

Page 35: ...3 D2 D1 D0 CTRL 9 0x0c000012 Res Res AC97 ENA FL_DIS FL_WP RW R W 0 R W 0 R W R W R W Table 15 PLD U6 Control Register 9 FL_WP Setting this bit disables writing the on board Flash on the phyCORE PXA25...

Page 36: ...D0 CTRL 11 0x0c000016 Res ALARM ACPRES ACSEL ACENA RW R W 0 R R R W R W Table 17 PLD U6 Control Register 11 ACENA Setting this bit turns on the battery charger controller ACSEL This bit selects the s...

Page 37: ...driver ICs are controlled by the PLD at U6 depending on the state of the current Chip Select signal A 0 2 5 F l a s h 1 6 b i t F l a s h 3 2 b i t F l a s h 3 2 b i t D 0 D 1 5 D 0 D 1 5 D 1 6 D 3 1...

Page 38: ...ling the additional functions such as TruIDE mode power and others I D E I n t e r f a c e U 7 P C M C I A D A T A A D D R E S S I n t e r r u p t s C o n t r o l C F C A R D F l a s h 3 2 b i t D 0 D...

Page 39: ...e hard disk will be attached to the board using spacers above of the phyCORE PXA255 module refer to Figure 14 for details FF UART BT UART Ethernet 2 USB Host USB Client Power Socket Inverter phyCORE P...

Page 40: ...their reset values are given in the following table REG ADDR D7 D3 D2 D1 D0 IDE 0 0x2001000 Res Res PM_5V RES RES Reset X IDE 1 0x2001002 Res DMA0 1 DMAEN RES IDE MEM Reset 0 0 0 IDE 2 0x2001004 Res R...

Page 41: ...D2 D1 D0 IDE 1 0x2001002 Res DMA0 1 DMAEN RES IDE MEM RW R W 0 R W R W R W 0 R 1 W 1 Table 20 IDE Control Register 1 IDE MEM Setting this bit to 1 selects the TrueIDE mode In this mode address line A...

Page 42: ...us line drivers IDEON Setting this bit turns on the control and address lines IDEIN Setting this bit turns on the input signals The IDE control register 4 is responsible for the supply voltage to the...

Page 43: ...signals is active A11 IDE_PCE1 and IDE_PCE2 Level 0 IDE_PCE1 active IDE_PCE2 not active 1 IDE_PCE2 active IDE_PCE1 not active Table 24 TrueIDE Memory Area Assignment Based on the above assignment sche...

Page 44: ...pansion Board The CompactFlash card is operated in TrueIDE mode The interface is decoupled from the buffered data and address bus on the Development Board with 74LVC245 line driver ICs P C M C I A C o...

Page 45: ...WR Reset 0 0 0 0 CF5 0x300100A Res VS2 VS1 BVD2 BVD1 Reset X X X X CF6 0x300100C Res WP Res CD2 CD1 Reset X X X Table 26 CF Card Control Register with Reset Values The operating states of the 5 V supp...

Page 46: ...D1 D0 CF1 0x3001002 Res Res Res Res IDE MEM RW R W 0 R W 0 R W 0 R W 0 R 1 W 1 Table 28 CF Card Control Register 1 IDE MEM Setting this bit to 1 turns on the TrueIDE mode writing a 0 selects the memo...

Page 47: ...ls CFCD Turns on the line driver with the CF card control output signals such as CD1 2 etc CF control register 4 configures the supply voltage for the CF card interface The register bit 5 V 3 V is use...

Page 48: ...e 32 CF Card Control Register 5 BVD1 Returns the CF card BVD1 signal BVD2 Returns the CF card BVD2 signal VS1 Returns the CF card VS1 signal VS2 Returns the CF card VS2 signal The CF card CD signals c...

Page 49: ...A255 External IRQ_Ethernet Figure 18 Ethernet Circuitry The Ethernet interface is accessible on the RJ45 socket at X23 The yellow LED extends to the LAN_LED_A signal and the green LED extends to LAN_L...

Page 50: ...physical memory area is given in the following table The address decoder generates the Ethernet CS at address 0x14000000 In addition an offset of 0x00000300 has to be added Ethernet Start Address CS_...

Page 51: ...ost interfaces are connected to a double USB host socket The first USB host interface can also operate in OTG mode and is also connected to an OTG socket on the Expansion Board The first USB host inte...

Page 52: ...P1362 USB OTG controller data sheet and user s manual for details 1 2 OTG_5V connected to 3 3V VDD_5V pin on ISP1362 2 3 X OTG_5V connected to 5V VDD_5V pin on ISP1362 JP6 This jumper configures the r...

Page 53: ...ith a USB client interface for communication with a PC The interface extends to a USB client socket X22 on the Development Board Ethernet 2 USB Host USB Client Power Socket AC97 IN MIC OUT Expansion B...

Page 54: ...Development Board for phyCORE PXA255 46 PHYTEC Me technik GmbH 2004 L 657e_0...

Page 55: ...1 5 S D R A M B a n k 0 F l a s h 3 2 b i t D 1 6 D 3 1 U 1 2 U 5 P X A 2 5 5 X 1 M M C C a r d 3 2 k H z U 2 0 R T C U 2 E G P I O U 1 9 C A N U 3 U S B Figure 23 Active TFT LCD Connection The Sharp...

Page 56: ...B 15 15 3 3V VCC 3 3V VCC 16 16 LCD_POS1 LCD_POS2 17 17 LCD_POS3 Table 36 LCD Connector at X33 The supply voltage for the TFT display and the inverter can be turned on with the help of a register in c...

Page 57: ...orted in the current version of the phyCORE PXA255 Two of the interfaces are accessible in the standard RS 232 level over DB 9 sockets at P1 FF UART and P2 BT UART Ethernet 2 USB Host USB Client Power...

Page 58: ...t Power Socket Inverter phyCORE PXA255 Touch Underside Connector Expan Board LCD Connectors IDE Interface JTAG Interface Matrix Keyboard AC97 Connector Reset Button GPIO Button MIC IN OUT AC97 AC97 AC...

Page 59: ...cated on the phyCORE module at U1 The RS 232 transceiver is configured for auto shutdown which means that the driver shuts off automatically after a few seconds in order to conserve power The RS 232 t...

Page 60: ...2 set to 3 4 and 5 6 The RS 232 transceiver is located on the Development Board Pin 5 GND Pin 9 nc Pin 4 nc Pin 8 BT_CTS Pin 3 BT_TxD Pin 7 BT_RTS Pin 2 BT_RxD Pin 6 nc Pin 1 nc Figure 28 P2 Pin Assig...

Page 61: ...elopment Board The IR UART extends to a 10 pin header connector at X19 to which an optional flat band cable with a DB 9 socket can be connected Signal A B Signal n c 1 1 n c STD_RxD 2 2 n c STD_TxD 3...

Page 62: ...Development Board for phyCORE PXA255 54 PHYTEC Me technik GmbH 2004 L 657e_0...

Page 63: ...N Connector The signals CAN RxD and CAN TxD are optically isolated from the phyCORE module over an ADU1402 opto coupler U45 and are converted over an 82C251 CAN transceiver U46 to CANH and CANL A swit...

Page 64: ...gures the CAN circuitry supply voltage open X CAN Ground from external source for optical isolation closed CAN Ground connected to on board Ground potential Table 40 CAN Interface Jumper Configuration...

Page 65: ...Touch Connect LCD Touch Panel RESET Button CAN Figure 31 Sound and Touch Controller Interfaces The sound decoder WM9712L is controlled via the controller s AC97 interface The SDATA_IN0 is used as the...

Page 66: ...A255 58 PHYTEC Me technik GmbH 2004 L 657e_0 Y T o u c h Y X X L I N E O U T L R M I C W o l f s o n A C 9 7 S o u n d C D L I N E I N L R O U T 2 R O U T 2 R F r o n t p l a t i n e M O N O O U T A C...

Page 67: ...U_TEMP battery temperature AUX 3 Light sensor Table 42 Voltage Supervision with WM9712L The sound portion of the WM9712L supports microphone mono stereo input und stereo output Sound Jack Functions X2...

Page 68: ...available on the Expansion Board and supports MultiMedia cards MultiMedia cards are available as memory devices with capacities of 8 to 256 MByte that can be easily removed by the user Access to the M...

Page 69: ...pulated on an Expansion Board These can be mounted in the housing at a 90 angle to the display whereby access to a MultiMediaCard CompactFlash USB and push buttons is possible MultiMediaCard CompactFl...

Page 70: ...e signals for the CompactFlash card The voltage pin CF_VCC can only be used for the CF card because it is switched on or off depending on the operating status of the socket Signal X30 Signal CF_VCC 1...

Page 71: ...VCC GND 3 4 GND CF_IORD 5 6 CF_CD1 CF_IOWR 7 8 CF_CD2 CF_IRQ 9 10 CF_RDY CF_RESET 11 12 CF_IOIS16 GND 13 14 GND OTG_ID 15 16 CF_BVD1 OTG_DP1 17 18 CF_BVD2 OTG_DM1 19 20 CF_LED OTG_VCC 21 22 CF_VS1 GN...

Page 72: ...Development Board for phyCORE PXA255 64 PHYTEC Me technik GmbH 2004 L 657e_0...

Page 73: ...Expansion Board and the Development Board serves as a reset button push button S1 is connected with the GPIO0 signal for both boards and can be used freely The 4 LEDs are controlled with a low level o...

Page 74: ...ocket Inverter phyCORE PXA255 Touch Underside Connector Expan Board LCD Connectors IDE Interface JTAG Interface Matrix Keyboard AC97 Connector Reset Button GPIO Button MIC IN OUT AC97 AC97 AC97 Expans...

Page 75: ...xtend to connector X4 and are arranged in columns and rows The column outputs have an in line resistance of 33R and the row inputs have an RC combination with R 1 kOhm against VCC and C 100 nF against...

Page 76: ...Development Board for phyCORE PXA255 68 PHYTEC Me technik GmbH 2004 L 657e_0...

Page 77: ...me of the phyCORE connector the expansion connector also uses a two dimensional number matrix Because of its different layout however the arrangement of the expansion connector s number matrix differs...

Page 78: ...6A CS_4 I O Chip Select signal of the processor can be used to access the USB controller alternative GPIO80 8A WE O Write enable signal for SDRAM SRAM and Flash devices Please note that the PWE signal...

Page 79: ...it signal alternative GPIO56 61A IOIS16 I O PCMCIA 16 bit access alternative GPIO57 63A PREG I O PCMCIA register control signal alternative GPIO55 64A LAN_CS I I O Chip Select for LAN controller 65A L...

Page 80: ...r alternative GPIO33 7B OE O Output enable signal of the processor 8B 10B 11B 12B 13B 15B 16B 17B 23B 25B 26B 27B 36B A0 A3 A5 A6 A8 A11 A13 A14 A16 A19 A21 A22 A25 I O Address lines 18B 20B 21B 22B 2...

Page 81: ...B OTG_INT2 I Interrupt INT2 signal USB controller 70B 71B 72B 73B 75B 76B 77B 78B 80B L_DD0 L_DD1 L_DD2 L_DD4 L_DD7 L_DD9 L_DD10 L_DD12 L_DD15 I O LCD data bus alternative GPIO 58 GPIO 59 GPIO 62 GPIO...

Page 82: ...3C ACRESET O RESET AC97 24C SYNC I O SYNC AC97 Alternative GPIO 31 25C BITCLK I O BITCLK Alternative GPIO 28 26C SDATA_IN_1 I O SDATA_IN 1 AC97 Interface Alternative GPIO 32 28C SDATA_IN_0 I O SDATA_I...

Page 83: ...IC 73C SSP_RXD I SPI RxD signal 74C SSP_TXD O SPI TxD signal 75C CS_EGPIO I SSP CS1 signal for MAX7301 EGPIO 76C CAN_CS I NSSP CS2 signal for MCP2515 CAN 78C CAN_INT O CAN Interrupt 79C CANRXD I O CAN...

Page 84: ...25D RS_RTS I FF UART RTS signal RS 232 26D RS_CTS I FF UART CTS signal RS 232 27D RS_DSR I FF UART DSR signal RS 232 28D RS_DTR O FF UART DTR signal RS 232 30D RS_RI I FF UART RI signal RS 232 31D RS...

Page 85: ...7301 IC with 7 interrupt capable inputs for connection to a matrix keyboard 71D SSP_EXTCLK I SSP external clock alternative GPIO 27 72D SSP_CLK O SSP clock signal alternative GPIO 23 73D SSP_SFRM I O...

Page 86: ...8A BUS11 30E 9A A1 BUS13 9A BUS13 30D 10A A2 BUS14 10A BUS14 30F 11A A4 BUS16 11A BUS16 31E 13A A7 BUS19 13A BUS19 32A 14A A9 BUS21 14A BUS21 32E 15A A10 BUS22 15A BUS22 32B 16A A12 BUS24 16A BUS24 33...

Page 87: ...44D 63A PREG BUS99 53A BUS83 45E 64A LAN_CS BUS101 54A BUS85 45D 65A LAN_DATA BUS102 55A BUS86 45F 66A LAN_RDY BUS104 56A BUS88 46E 68A L_PCLK BUS107 58A BUS91 47A 69A L_LCLK BUS109 59A BUS93 47E 70A...

Page 88: ...DQM_3 BUS55 35B BUS55 39B 36B A25 BUS57 36B BUS57 39F 37B D16 BUS58 18B BUS28 33F 38B D17 BUS60 20A BUS30 34E 40B D21 BUS63 21B BUS33 34F 41B D23 BUS65 23A BUS35 35E 42B D24 BUS66 28B BUS44 37C 43B D...

Page 89: ...2B 8C H_OC1 PFO 8C PFO 3E 9C H_OC2 BOOT BOOT 9C BOOT BOOT 3B 10C RESIN HDRESET 10C RESET 3D 11C RESET_OUT PORESET 11C RESOUT 4E 13C NSSP_SFRM GPIO2 13C GPIO2 4F 14C NSSP_CLK GPIO4 14C GPIO4 5C 15C NS...

Page 90: ...IO47 14A 48C GPIO_4 GPIO58 43C GPIO50 14F 49C GPIO_7 GPIO60 44C GPIO52 15C 50C GPIO_10 GPIO61 45C GPIO53 15E 51C GPIO_12 GPIO63 46C GPIO55 15F 53C GPIO_21 GPIO66 48C GPIO58 16E 54C EGPIO0 GPIO68 49C G...

Page 91: ...P_PEN GPIO16 21D GPIO16 7D 22D RS_RXD GPIO17 22D GPIO17 7F 23D RS_TXD GPIO19 23D GPIO19 8E 25D RS_RTS GPIO22 25D GPIO22 8F 26D RS_CTS GPIO24 26D GPIO24 9E 27D RS_DSR GPIO25 27D GPIO25 9B 28D RS_DTR GP...

Page 92: ...GPIO65 17F 56D EGPIO4 GPIO72 53D GPIO67 18E 57D EGPIO5 GPIO73 55D GPIO70 18F 58D EGPIO7 GPIO75 56D GPIO72 19E 60D EGPIO10 61D EGPIO12 62D EGPIO13 63D EGPIO15 65D EGPIO19 66D EGPIO20 67D EGPIO21 68D EG...

Page 93: ...to an ARM compatible dual row 20 pin connector at X254 This connector is located on the left side above the phyCORE module The following table describes the pin assignment for the JTAG interface Signa...

Page 94: ...Development Board for phyCORE PXA255 86 PHYTEC Me technik GmbH 2004 L 657e_0...

Page 95: ...esented in Figure 40 PHYTEC is currently working on an enclosure for this Development Board with Expansion Board The dimensions shown below are subject to change The maximum height of all components t...

Page 96: ...x 170 mm Dimensions Expansion Board 35 mm x 150 mm Weight approximately 1000 grams Storage temperature 0 C to 85 C Operating temperature 0 C to 70 C Humidity 95 r F not condensed Operating voltage 8 V...

Page 97: ...ts can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds Caution If any modifications to the module are performed regardless of their nature the...

Page 98: ...Development Board for phyCORE PXA255 90 PHYTEC Me technik GmbH 2004 L 657e_0...

Page 99: ...ement Diagram PHYTEC Me technik GmbH 2004 L 657e_0 91 21 Component Placement Diagram Figure 42 Component Placement Diagram Development Board PCB Revision 1220 1 Figure 43 Component Placement Diagram E...

Page 100: ...r phyCORE PXA255 92 PHYTEC Me technik GmbH 2004 L 657e_0 22 Revision History Date Version numbers Changes in this manual 03 Oct 2004 Manual L 657e_0 PCM 990 PCB 1220 1 1220 2 PCM 985 PCB 1222 1 First...

Page 101: ...Appendices PHYTEC Me technik GmbH 2004 L 657e_0 93 Appendices A AI Hardware Revision...

Page 102: ...Development Board for phyCORE PXA255 94 PHYTEC Me technik GmbH 2004 L 657e_0...

Page 103: ...Supply Voltage 39 CF LED 37 CF3V 39 CF5V 39 CFIN 39 CFOE 39 CFON 39 Compact Flash Interface 36 CompactFlash 36 Control PLD 21 D Data Address Bus 29 E ESD 1 Ethernet 42 Ethernet CS 43 Expansion Board 6...

Page 104: ...MMC 61 MultiMedia Card 61 O OTG 44 Overview of the Development Board 7 P Physical Dimensions 88 PLD 30 Port Pin Initialization 9 Power System 15 Push Button 66 PWAIT 38 R RDY 38 RDYENA 38 Removable Ju...

Page 105: ...CORE PXA255 Document number L 657e_0 Preliminary Edition November 2004 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address...

Page 106: ...Published by PHYTEC Me technik GmbH 2004 Ordering No L 657e_0 Printed in Germany...

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