Phytec phyCORE-PXA255, Hardware Manual

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Memory Configuration
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PHYTEC Meßtechnik GmbH 2004 L-657e_0
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5.2.2 External Data and Address Bus
The data and address bus on the phyCORE-PXA255 operates with a
clock frequency of 100 MHz, therefore it must be decoupled for
external use. All components on the Development Board except the
Control PLD are connected to the decoupled data and address bus.
The driver ICs are controlled by the PLD at U6 depending on the state
of the current Chip Select signal.
A 0 - 2 5
F l a s h 1 6 - b i t
F l a s h 3 2 - b i t
F l a s h 3 2 - b i t
D 0 - D 1 5
D 0 - D 1 5
D 1 6 - D 3 1
D 0 - D 1 5
D 1 6 - D 3 1
U 1 0
U 1 2
U 1 1
U 1 3
U 1 5
U 5
U 1 2
U 2
U 3
U 6
X 1
P X A 2 5 5
V C C _ C O R E
M M C - C a r d
R S - 2 3 2
3 2 k H z
S D R A M
B a n k 0
S D R A M
B a n k 0
T o u c h c o n t r .
E G P I O
U 8
D 0 - 1 5
C o n t r o l
X D 0 - 1 5
X A 0 - 2 5
C o n t r o l
D 1 6 - 3 1
C o n t r o l
X D 1 6 - 3 1
Figure 12: Decoupling the Data and Address Bus