Phytec phyCORE-PXA255, Hardware Manual

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Memory Configuration
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PHYTEC Meßtechnik GmbH 2004 L-657e_0
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5.2 Control PLD (U6)
Control PLD U6 controls the drivers for the buffered data and the
address bus. Furthermore, all power management, control and
interrupt functions, except for the CF card and the IDE interface are
contained as well. The individual functions will be explained in
greater detail in the register description.
A D D R E S S
D E C O D E R
U 6
/ C S 2 . . / C S 5
D A T A
A D D R E S S
I n t e r r u p t s
P o w e r
X - B U S
L E D s
D e t e c t
/ C S 2
C o n t r o l
F l a s h 3 2 - b i t
D 0 - D 1 5
V C C _ C O R E
U 1 0
D 0 - D 1 5
U 1 3
S D R A M
B a n k 0
D 1 6 - D 3 1
U 1 5
S D R A M
B a n k 0
F l a s h 3 2 - b i t
D 1 6 - D 3 1
U 1 2
U 5
P X A 2 5 5
X 1
M M C - C a r d
3 2 k H z
U 2 0
R T C
U 2
E G P I O
U 1 9
C A N
U 3
U S B
Figure 11: Control PLD U6
5.2.1 Control PLD (U6) Registers
Control PLD U6 is addressed over the PXA255’s Chip Select signal
/CS_3. The bus width is set to 16-bit as a VLIO interface. The
registers of the Control PLD are listed in the following table. The
register's reset value after the system start is shown below the
description.