Phytec phyCORE-PXA255, Hardware Manual

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Memory Configuration
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PHYTEC Meßtechnik GmbH 2004 L-657e_0
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5 Memory Configuration
The Development Board for the phyCORE-PXA255 uses the /CS
signals /CS2 and /CS3 as well as the PCMCIA interface for
controlling the components on the data bus. The other /CS signals on
the phyCORE-PXA255 are controlled by the address decoder (control
PLD U7) in order to connect the data bus driver. The PCMCIA
interface is managed by the second address decoder (Control PLD
U6), which generates all necessary signals for the CF card and the
IDE interface.
/CS0 2 * 16-bit Flash memory 16 to 64 MByte asynchronous /
synchronous (optional 16-bit Flash memory 8 MByte
asynchronous)
/CS1 free (pre-configured 16-bit asynchronous ROM/RAM)
/CS2 16-bit VLIO interface, expansion connector X17 on the
Development Board
/CS3 16-bit VLIO interface, address decoder U7 on the
Development Board
/CS4 USB host with 16-bit VLIO interface on th
phyCORE-PXA255 module
/CS5 Ethernet chip with 32-bit VLIO interface on the
phyCORE-PXA255 module
The SDRAM /CS signals extend to the Development Board (X23) but
are not used. Depending on the phyCORE-PXA255 configuration
option, these /CS signals /SDCS_0 through /SDCS_3 are connected
with the chips of both SDRAM banks.
/SDCS_0 64 MB 2*16-bit SDRAM on the phyCORE-PXA255
/SDCS_1 optional 64 MB 2*16-bit SDRAM on the
phyCORE-PXA255
/SDCS0/1 optional 128 MB 2*16-bit SDRAM on the
phyCORE-PXA255
/SDCS2/3 optional 128 MB 2*16-bit SDRAM on the
phyCORE-PXA255