Phytec phyCORE-MPC5200B tiny, Hardware Manual

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phyCORE-MPC5200B tiny
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PHYTEC Messtechnik GmbH 2006 L-678e_0
6.2 DDR SDRAM
The phyCORE-MPC5200B tiny is equipped with fast D ouble D ata
R ate S ynchronous D ynamic R andom A ccess M emory
(DDR SDRAM) devices. This memory is connected to a dedicated
SDRAM interface provided by the MPC5200B processor.
The DDR SDRAM memory bank consist of two 16-bit data port
devices connected in parallel to support the 32-bit bus width of the
processor. The memory bank is controlled by Chip Select signal
/SD_CS0 of the processor's DDR SDRAM controller.
Table 6 shows all possible memory configurations.
Available Capacity Device Organization Devices (two)
32 MByte 128 MBit
2 MBit x 16 x 4 banks MT46V8M16
TSOP66 packaging
64 MByte 256 MBit
4 MBit x 16 x 4 banks MT46V16M16
TSOP66 packaging
128 MByte 512 MBit
8 MBit x 16 x 4 banks MT46V32M16
TSOP66 packaging
Table 6: DDR SDRAM Device Selection