Phytec phyCORE-MPC5200B tiny, Hardware Manual

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phyCORE-MPC5200B tiny
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PHYTEC Messtechnik GmbH 2006 L-678e_0
6.1 Flash Memory
Use of Flash as non-volatile memory on the phyCORE-MPC5200B
tiny provides an easily reprogrammable means of code storage.
•
16 MByte Intel Strata Flash memory
•
16-bit bus width
•
Only asynchronous operation is possible
The Flash memory bank supports the following Intel memory devices:
Type Size Manufacturer Device Code Manufacturer Code
Asynchronous Devices
28F128J3 16 MByte Intel 0x0018 0x0089
Table 5: Choice of Flash Memory Devices and Manufacturers 1
The organization of the Flash memory bank is 16-bit. The Flash
memory bank is controlled by the processor Chip Select signal /CS0.
This Chip Select signal is the dedicated control signal for boot
purposes.
The MPC5200B's LocalPlus bus can be configured for many different
bus modes. For /CS0 the 25-bit address / 16-bit data multiplexed mode
was chosen because it offers the largest address space without
interfering the ATA or PCI bus. With 25 address lines a total of
32 MByte of data/code can be addressed. It is possible to use different
bus modes on other available Chip Select signals.
The Flash memory bank 0 starts at address 0x0000_0100 or
0xFFFF_0100 depending on the startup configuration and relative to
the base address of the processor's Chip Select signal /CS0.
The access speed depends on the equipped memory device. The
LocalPlus Bus clock cycle is determined by the PCI clock which is
configured by the PCI clock divider. A typical configuration selects
66 MHz. The resulting basic cycle time is 15.15 ns.
1
: Flash types in the shaded lines are the preferred parts for the phyCORE-MPC5200B tiny.