Phytec phyCORE-LPC2292/94, Hardware Manual

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phyCORE-LPC2292/94
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PHYTEC Messtechnik GmbH 2006 L-658e_5
Configuration of the LPC2292/94 controller's Chip Select signals is
only possible in a restricted matter. This is due to hardware defined
address ranges for the individual /CS signals. Only bus access time
and access type can be coinfigured with the bus configuration registers
BCFG0 to BCFG3.
The following table shows the predefined address ranges for the
individual /CS signals (banks) and the corresponding bus
configuration registers.
Bank Address Range Configuration Register
0 8000 0000 – 80FF FFFF BCFG0
1 8100 0000 – 81FF FFFF BCFG1
2 8200 0000 - 82FF FFFF BCFG2
3 8300 0000 - 83FF FFFF BCFG3
Table 38: /CS Signal (Bank) Address Ranges and Configuration Registers
The following image depicts the default memory model on the Philips
LPC2292/94 microcontroller showing internal and external address
spaces of the controller. This memory model also applies to the
phyCORE-LPC2292/94 module.