Phytec phyCORE-i.MX31, Hardware Manual

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System Memory
©
PHYTEC Messtechnik GmbH 2007 L-700e_0
9
Note:
SL is short for Signal Level (V) and is the applicable logic level to interface a given
pin.
Those pins marked as “N/A” have a range of applicable values that constitute proper
operation.
Table 1: Pin-out of the phyCORE-Connector X1
P
IN
R
OW
X1A
P
IN
# S
IGNAL
I/O SL D
ESCRIPTION
1A NVCC_7 O NVCC_7 LCD reference voltage (1,5V-3,0V )
2A GND - 0 Ground 0V
3A x_LC_SD_D_CLK O NVCC_7 LCD serial interface clock
4A x_LC_PAR_RS O NVCC_7 Data/command select for parallel LCD interface
5A x_LC_VSYNC0 I/O NVCC_7 Display 0 vertical synchronization pulse
6A x_LC_READ O NVCC_7 System-80: READ
System 68K: ENABLE
In byte enable mode
System-80: READ_L
System-68K: ENABLE_L
7A GND - 0 Ground 0V
8A x_LC_D3_REV O NVCC_7 REV signal for Sharp display 3
9A x_LC_ D3_SPL O NVCC_7 SPL signal for Sharp display 3
10A x_LC_ DRDY0 O NVCC_7 Keyboard row 4 scan output pin of the µC
11A x_LC_FPLINE O NVCC_7 Display 3 horizontal synchronization pulse
(FPLINE/HSYNC/LP)
12A GND - 0 Ground 0V
13A x_LC_D0 I/O NVCC_7 Input/Output data to display.
14A x_LC_D2 I/O NVCC_7 Input/Output data to display.
15A x_LC_D3 I/O NVCC_7 Input/Output data to display.
16A x_LC_D5 I/O NVCC_7 Input/Output data to display.
17A GND - 0 Ground 0V
18A x_LC_D8 I/O NVCC_7 Input/Output data to display.
19A x_LC_D10 I/O NVCC_7 Input/Output data to display.
20A x_LC_D11 I/O NVCC_7 Input/Output data to display.
21A x_LC_D13 I/O NVCC_7 Input/Output data to display.
22A GND - 0 Ground 0V
23A x_LC_D17 O NVCC_7 Output data to display.
In byte enable mode, READ_H (for sys80) or
ENABLE_H (for sys68k)
24A x_/CS0 O 3.3V /CS0 output (per default used by NOR-Flash)
25A x_/CS1 O 3.3V /CS1 output (per default used by Ethernet)
26A x_/CS4 O 3.3V /CS4 output (per default used by SRAM)
27A GND - 0 Ground 0V