Phytec miniMODUL-537, Hardware Manual

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The Optional Real-Time Clock RTC72421
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PHYTEC Meßtechnik GmbH 1993 L-006e_2
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11.4 Description of the Control-Bits
The exact description of the RTC would exceed the scope of this
documentation. Please use the corresponding data sheets of this chip
or ask us in case of problems.
HOLD
HOLD has to be set immediately before the access of the time/date
registers. After termination of all write or read accesses, HOLD has to
be disabled again.
This operation should take place within one second.
BUSY
This bit can be read only. Access to registers should take place only if
BUSY is LOW. BUSY is always HIGH, when HOLD is not HIGH.
After setting of HOLD , BUSY is LOW at the latest after 190 µsec.
MASK
This bit prevents the LOW level at the pulse-output, when it is
enabled. For the application with standard pulse, MASK has to be
erased.
ITRPT/STND
This bit selects the pulse-output between interrupt-mode and
fixed-mode. The interrupt mode is not described here. This bit should
be LOW. This results in the fixed-pulse mode with a duration of
7.8123 msec.
REST
This bit is set to erase the counter of the second-ratios. The ratio
counter is on hold, as long as REST is HIGH. The counter must be
enabled by erasing this bit.
STOP
Setting STOP stops the counter completely. The clock starts at the
latest 122 µsec after erasing this bit.