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Phytec 1488.2, Hardware Manual

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PCM-065/phyCORE-i.MX8X System on Module 

 

 L-864e.A1 

 

 

 

 

 

© PHYTEC America LLC, 2021 

 

53 

9.2

 

Parallel LCD Display 

The  phyCORE-i.MX8X  SOM  provides  a 1×  24-bit  Parallel  LCD  display  port  with  up  to  720p60  resolution.  It 
supports the following display interface modes: 

•

 

Parallel LCD: RGB 8/16/18/24-bit data output 

•

 

ITU-R BT.656 mode: progressive-to-interlace feature and RGB to YCbCr 4:2:2 color space conversion to 
support 525/60 and 625/50 operation. 

The locations of the LCD display signals at the phyCORE-Connector are listed in the table below. 

Table 42.  Parallel Display Connections at the phyCORE-Connector 

X1 
Pin # 

Processor 
Signal 

SOM Signal 

Type 

Level 

Processor 
Ball 

Description 

B39 

LCD_D0 

X_ESAI0_FSR/ENET1_RGMII_TXC 

O 

1.8V 

B26 

LCD Data 0 

B38 

LCD_D1 

X_ESAI0_FST/ENET1_RGMII_TXD2 

O 

1.8V 

E23 

LCD Data 1 

B42 

LCD_D2 

X_ESAI0_SCKR/ENET1_RGMII_TX_CTL 

O 

1.8V 

H22 

LCD Data 2 

B41 

LCD_D3 

X_ESAI0_SCKT/ENET1_RGMII_TXD3 

O 

1.8V 

C25 

LCD Data 3 

B43 

LCD_D4 

X_ESAI0_TX0/ENET1_RGMII_RXC 

O 

1.8V 

G23 

LCD Data 4 

B44 

LCD_D5 

X_ESAI0_TX1/ENET1_RGMII_RXD3 

O 

1.8V 

E25 

LCD Data 5 

B46 

LCD_D6 

X_ESAI0_TX2_RX3/ENET1_RGMII_RXD2 

O 

1.8V 

C27 

LCD Data 6 

B47 

LCD_D7 

X_ESAI0_TX3_RX2/ENET1_RGMII_RXD1 

O 

1.8V 

D24 

LCD Data 7 

B48 

LCD_D8 

X_ESAI0_TX4_RX1/ENET1_RGMII_TXD0 

O 

1.8V 

B28 

LCD Data 8 

B49 

LCD_D9 

X_ESAI0_TX5_RX0/ENET1_RGMII_TXD1 

O 

1.8V 

K22 

LCD Data 9 

B51 

LCD_D10 

X_SPDIF0_RX/ENET1_RGMII_RXD0 

O 

1.8V 

F24 

LCD Data 10 

B52 

LCD_D11 

X_SPDIF0_TX/ENET1_RGMII_RX_CTL 

O 

1.8V 

J23 

LCD Data 11 

B53 

LCD_D12 

X_SPDIF0_EXT_CLK/ENET1_REFCLK_12
5M_25M 

O 

1.8V 

E27 

LCD Data 12 

B57 

LCD_D13 

X_SPI3_SCK 

O 

1.8V 

D28 

LCD Data 13 

B59 

LCD_D14 

X_SPI3_SDO 

O 

1.8V 

G25 

LCD Data 14 

B58 

LCD_D15 

X_SPI3_SDI 

O 

1.8V 

H24 

LCD Data 15 

A58 

LCD_D16 

X_UART1_RTS_B 

O 

1.8V 

G29 

LCD Data 16 

A57 

LCD_D17 

X_UART1_CTS_B 

O 

1.8V 

G27 

LCD Data 17 

A33 

LCD_D18 

X_SAI0_TXD 

O 

1.8V 

K34 

LCD Data 18 

A35 

LCD_D19 

X_SAI0_TXC 

O 

1.8V 

J35 

LCD Data 19 

A32 

LCD_D20 

X_SAI0_RXD 

O 

1.8V 

M34 

LCD Data 20 

A37 

LCD_D21 

X_SAI1_RXD 

O 

1.8V 

M32 

LCD Data 21 

A38 

LCD_D22 

X_SAI1_RXC 

O 

1.8V 

L35 

LCD Data 22 

A39 

LCD_D23 

X_SAI1_RXFS 

O 

1.8V 

N35 

LCD Data 23 

A28 

LCD_HSYNC 

X_SPI0_CS1 

O 

1.8V 

R35 

LCD Horizontal 
Sync 

B55 

LCD_RESET 

X_SPI3_CS0 

I 

1.8V 

D26 

LCD Reset 

B56 

LCD_EN 

X_SPI3_CS1 

I 

1.8V 

F28 

LCD Enable 

A54 

LCD_VSYNC 

X_MCLK_IN1 

O 

1.8V 

M22 

LCD Vertical 
Sync 

A53 

LCD_CLK 

X_MCLK_IN0 

I 

1.8V 

L23 

LCD Clock 

A55 

LCD_PWM 

X_MCLK_OUT0 

O 

1.8V 

K24 

LCD PWM 

 

Summary of Contents for 1488.2

Page 1: ...A product of a PHYTEC Technology Holding company phyCORE i MX8X Hardware Manual Document No L 864e A1 SOM Prod No PCM 065 SOM PCB No 1488 2 CB Prod No PCM 942 CB PCB No 1491 1 Edition Feb 2021...

Page 2: ...bility whatsoever for consequential damages resulting from the use of this manual or its associated product PHYTEC reserves the right to alter the information contained herein without prior notificati...

Page 3: ...gram 17 6 Technical Specifications 20 7 Electrical Specifications 21 8 Minimum Requirements for Operation 22 9 Solder Jumpers 23 1 1 Solder Jumper Locations 25 2 Pin Descriptions 27 2 1 Pinout Tables...

Page 4: ...2 UART0 51 9 Display Interfaces 52 9 1 LVDS MIPI DSI 52 9 2 Parallel LCD Display 53 10 Camera Interfaces 54 10 1 MIPI CSI 54 10 2 Parallel Camera Input Port 54 11 Peripheral Interfaces 55 11 1 ADC 55...

Page 5: ...Component Placement processor side 18 Figure 3 phyCORE i MX8X Component Placement connector side 19 Figure 4 Three Position Solder Jumper Pad Numbering Scheme 23 Figure 5 Pinout of the phyCORE Connec...

Page 6: ...MLB Connections at the phyCORE Connector 45 Table 24 PCIe Connections at the phyCORE Connector 45 Table 25 SAI0 Connections at the phyCORE Connector 45 Table 26 SAI1 Connections at the phyCORE Connec...

Page 7: ...Connector 57 Table 51 GPIO3 Accessibility at phyCORE Connector 57 Table 52 GPIO4 Accessibility at phyCORE Connector 58 Table 53 GPIO5 Accessibility at phyCORE Connector 58 Table 54 GPT Signals 59 Tab...

Page 8: ...System On Module PHYTEC System on Modules SOM and Single Board Computers SBC henceforth collectively referred to as products are designed as subcomponents for integration in electrical devices Combine...

Page 9: ...ge in version control to accommodate new or obsolete parts Instead PHYTEC manages this at the SOM level PHYTEC ensure continued availability of pin and function compatible SOMs and SBCs further minimi...

Page 10: ...gh level signal The hex numbers given for addresses of I2 C devices always represent the 7 most significant bits MSB of the address byte The correct value of the least significant bit LSB will depend...

Page 11: ...ference to the available user buttons or DIP Switches on the carrier board UART Universal Asynchronous Receiver Transmitter Signal Types Different types of signals are brought out at the phyCORE Conne...

Page 12: ...A1 PHYTEC America LLC 2021 12 PCIe Input Differential line pairs 100 Ohm PCIe level input PCIe_I PCIe Output Differential line pairs 100 Ohm PCIe level output PCIe_O MIPI CSI 2 Input Differential lin...

Page 13: ...hieve their small size through SMD technology and multi layer PCB designs In accordance with the complexity of the module 0201 packaged SMT components and laser drilled micro vias are also used and pr...

Page 14: ...3 0 card 2x 32KB I2 C EEPROM 2x MIPI or LVDS display 1x 18 bit parallel LCD display 1x 16 bit parallel CSI camera 1x MIPI CSI camera with 4 lanes 1x Independent 1 lane PCIe Gen3 with L1 substate suppo...

Page 15: ...PCM 065 phyCORE i MX8X System on Module L 864e A1 PHYTEC America LLC 2021 15 3 Block Diagram Figure 1 phyCORE i MX8X Block Diagram...

Page 16: ...tallest component on the top processor to the tallest component on the bottom phyCORE Connectors The maximum component height excluding the connector X1 is approximately 1 0 mm on the bottom connecto...

Page 17: ...17 5 Component Placement Diagram The phyCORE i MX8X component placement diagrams presented in this manual Figure 2 and Figure 3 are for quick reference only Visit our Hardware Documentation Page for...

Page 18: ...PCM 065 phyCORE i MX8X System on Module L 864e A1 PHYTEC America LLC 2021 18 Figure 2 phyCORE i MX8X Component Placement Processor Side...

Page 19: ...PCM 065 phyCORE i MX8X System on Module L 864e A1 PHYTEC America LLC 2021 19 Figure 3 phyCORE i MX8X Component Placement Connector Side...

Page 20: ...6 Technical Specifications Table 3 Technical Specifications Specification Dimensions 52 mm x 42 mm x 4 8 mm Mass 16 65g Storage Temperature 25C to 85C Operating Temperature 25C to 85C Humidity TBD Typ...

Page 21: ...SD card 581 mA Measured while testing the following interfaces devices simultaneously via a python test script in Linux Two LCD displays plugged in and four instances of the following command were run...

Page 22: ...OM Implement at least one of the supported boot devices to support loading and executing application software Refer to the i MX8X Processor Reference Manual for details regarding all supported boot mo...

Page 23: ...omains to meet application requirements These domains are detailed in Table 5 Table 5 Voltage Domain Configurations Voltage Domain Jumper Associated Signals VDD_EMMC0 J10 EMMC_CLK NAND_READY_B EMMC_CM...

Page 24: ...n to VCC_IO_3V3_1V8 J9 Sets VDD_USDHC1_VSELECT Domain 0 Ohm 1 2 Sets the VDD_USDHC1_VSELECT domain to 1 8V 2 3 Sets the VDD_USDHC1_VSELECT domain to 3 3V J10 Sets VDD_EMMC0 Domain 0 Ohm 1 2 Sets the V...

Page 25: ...PCM 065 phyCORE i MX8X System on Module L 864e A1 PHYTEC America LLC 2021 25 1 1 Solder Jumper Locations Figure 5 Jumper Locations Processor Side...

Page 26: ...PCM 065 phyCORE i MX8X System on Module L 864e A1 PHYTEC America LLC 2021 26 Figure 6 Jumper Locations Connector Side...

Page 27: ...type also includes information about the signal direction CAUTION The NXP Semiconductor i MX8X is a multi voltage operated microprocessor and as such special attention should be paid to the interface...

Page 28: ...ave multiple muxable functions As most of these pins are connected directly to the phyCORE Connector the alternative functions are available by using the phyCORE i MX8X SOM s pin muxing options Signal...

Page 29: ...a 1 A16 X_USDHC1_DATA0 NAND_CE1_B I O 3 3VJ11 A27 USDHC1 Data 0 A17 GND Ground A18 X_USDHC1_CLK O 3 3VJ11 G23 USDHC1 Clock A19 X_USDHC1_CMD O 3 3VJ11 C25 USDHC1 Command A20 GND Ground A21 X_SPI2_CS0 I...

Page 30: ...3V H14 USB3 Super Speed 3 Transmission Control 1 B9 GND Ground B10 X_USB3_SS3_TC2 I O 3 3V G15 USB3 Super Speed 3 Transmission Control 2 B11 X_USB3_SS3_TC3 I O 3 3V C15 USB3 Super Speed 3 Transmissio...

Page 31: ...V AL31 Bootmode pin 2 B36 X_BOOT_MODE3 I O 1 8V AJ29 Bootmode pin 3 B37 GND Ground B38 X_ESAI0_FST ENET1_RGMII_TXD2 O 1 8V E23 ENET1 RGMII Transmit Data 2 B39 X_ESAI0_FSR ENET1_RGMII_TXC O 1 8V B26 EN...

Page 32: ...3 3V AD32 MIPI DSI0 GPIO 0 C14 X_MIPI_DSI0_GPIO0_01 I O 3 3V AE35 MIPI DSI0 GPIO 1 C15 GND Ground C16 X_MIPI_DSI0_DATA3_N O Differential AJ15 MIPI DSI0 Data 3 Negative C17 X_MIPI_DSI0_DATA3_P O Diffe...

Page 33: ...MIC Interupt C60 X_PMIC_WDI I 1 8V PMIC Watchdog Input C61 X_SCU_GPIO0_00 I O 1 8V Y22 System Control Unit GPIO 0 C62 X_SCU_GPIO0_01 I O 1 8V AC25 System Control Unit GPIO 1 C63 GND Ground C64 VCC_1V8...

Page 34: ...I0_DATA3_N I Differential AN19 MIPI CSI0 Data 3 Negative D40 GND Ground D41 X_MIPI_CSI0_DATA1_P I Differential AP20 MIPI CSI0 Data 1 Positive D42 X_MIPI_CSI0_DATA1_N I Differential AM20 MIPI CSI0 Data...

Page 35: ...C PWR_I 3 3V Main Power Supply Input D70 VCC PWR_I 3 3V Main Power Supply Input J6 The voltage level for this signal is configurable for 1 8V or 3 3V via J6 The default voltage level is listed here bu...

Page 36: ...o backup the Secure Non Volatile Storage which includes the RTC a secondary voltage source of 3V can be supplied to the phyCORE i MX8X SOM at the VBAT pin pin C66 of phyCORE Connector X1 The PMIC goes...

Page 37: ...Table 13 Internal Voltage Rails Schematic Signal Voltage V Function VCC_SNVS 3 0 i MX8X Secure Non Volatile Storage VCC_MAIN 1 0 i MX8X Core VCC_GPU 1 1 i MX8X GPU VCC_CPU 1 1 i MX8X CPU VCC_DDRIO 1 1...

Page 38: ...t address 0x52 0x56 4 3 eMMC Flash An eMMC flash device is populated at U4 as a programmable nonvolatile storage The eMMC flash is connected to the EMMC0 8 bit interface of the i MX8X which supports e...

Page 39: ...e 0 USDHC1_DATA1 NAND_RE_B O 3 3VJ10 B26 NAND Read Enable USDHC1_DATA0 NAND_CE1_B O 3 3VJ10 A27 NANE Chip Enable 11 USDHC1_DATA3 NAND_ALE O 3 3VJ10 E25 NAND Address Latch Enable USDHC1_DATA2 NAND_WE_B...

Page 40: ...on board eMMC at U4 The USDHC1 port provides a 4 bit wide data bus that supports embedded MultiMedia Card 5 1 SD Host Processor Standard Specification 3 0 SD Physical Layer Specification v3 0 UHS I SD...

Page 41: ...purposes the BOOTMODE pins are available at the phyCORE Connector These signals are strapped to default values using on board resistors The default configuration is 0010 and the default setting is to...

Page 42: ...10 BASE Te 100BASE TX and 1000BASE T protocols to interface directly to twisted pair media through an external transformer CAUTION Only ENET0 is translated with a DP83867 The ENET1 signals are not It...

Page 43: ...SCKT ENET1_RGMII_TXD3 O 3 3V C25 ENET1 RGMII Transmit Data 3 B42 X_ESAI0_SCKR ENET1_RGMII_TX_CTL O 3 3V H22 ENET1 RGMII Transmit Control B43 X_ESAI0_TX0 ENET1_RGMII_RXC I 3 3V G23 ENET1 RGMII Receive...

Page 44: ...X_MIPI_DSI0_I2C0_SCL OD O 3 3V W27 MIPI DSI0 I2C0 Clock C11 MIPI DSI0 I2C0 SDA X_MIPI_DSI0_I2C0_SDA OD I O 3 3V V22 MIPI DSI0 I2C0 Data C41 MIPI DSI1 I2C0 SCL X_MIPI_DSI1_I2C0_SCL OD O 3 3V AE33 MIPI...

Page 45: ...Request B31 X_PCIE_CTRL_WAKE_B 3 3V A11 PCIe Link Reactivation 6 6 SAI and ESAI The phyCORE i MX8X SOM provides four Serial Audio Interfaces SAI and an Enhanced Serial Audio Interface ESAI The SAI mo...

Page 46: ...M22 Audio DMA Master Clock IN1 A55 MCLK_OUT0 X_MCLK_OUT0 O 3 3V K24 Audio DMA Master Clock Out Table 30 ESAI0 Connections at the phyCORE Connector X1 Pin Processor Signal SOM Signal Type Level Proces...

Page 47: ...ock A26 SPI0_CS0 X_SPI0_CS0 I O 3 3V R33 SPI0 Chip Select 0 A28 SPI0_CS1 X_SPI0_CS1 I O 3 3V R35 SPI0 Chip Select 1 A29 SPI0_SDO X_SPI0_SDO O 3 3V R31 SPI0 Data Out A30 SPI0_SDI X_SPI0_SDI I 3 3V P34...

Page 48: ...ration The USB 2 0 module is compliant with On The Go OTG supplement and the USB 3 0 is compliant with the USB 3 0 and USB 2 0 with OTG supplement specification USB1 is a separate independent USB 2 0...

Page 49: ...G Connections at the phyCORE Connector X1 Pin SOM Signal Type Level Processor Ball Description B1 USB_OTG2_VBUS A I 5V H16 USB OTG2 VBUS input B2 X_USB_OTG2_ID A I 3 3V F16 USB OTG2 2 0 Dual Role Devi...

Page 50: ...M4F GPIO3 D61 M4F_GPIO4 X_ADC_IN4 I O 1 8V W29 M4F GPIO4 D61 M4F_TPM_CH0 X_ADC_IN4 O 1 8V W29 M4F Temperature Monitor Channel 0 D64 M4F_GPIO5 X_ADC_IN5 I O 1 8V V34 M4F GPIO5 D64 M4F_TPM_CH1 X_ADC_IN...

Page 51: ...ble 39 JTAG Connections at the phyCORE Connector X1 Pin SOM Signal Type Level Processor Ball Description D51 X_JTAG_TCK I 1 8V AE31 JTAG Test Clock D52 X_JTAG_TDO O 1 8V AF32 JTAG Test Data Output D53...

Page 52: ...Data 1 Positive C21 X_MIPI_DSI0_DATA0_N O Differential AJ21 LVDS0 MIPI DSI0 Data 0 Negative C22 X_MIPI_DSI0_DATA0_P O Differential AK22 LVDS0 MIPI DSI0 Data 0 Positive C23 X_MIPI_DSI0_DATA2_N O Differ...

Page 53: ...I0_TX2_RX3 ENET1_RGMII_RXD2 O 1 8V C27 LCD Data 6 B47 LCD_D7 X_ESAI0_TX3_RX2 ENET1_RGMII_RXD1 O 1 8V D24 LCD Data 7 B48 LCD_D8 X_ESAI0_TX4_RX1 ENET1_RGMII_TXD0 O 1 8V B28 LCD Data 8 B49 LCD_D9 X_ESAI0...

Page 54: ...I0 Data 2 Positive D49 X_MIPI_CSI0_DATA2_N I Differential AN23 MIPI CSI0 Data 2 Negative D38 X_MIPI_CSI0_DATA3_P I Differential AR19 MIPI CSI0 Data 3 Positive D39 X_MIPI_CSI0_DATA3_N I Differential AN...

Page 55: ...vel Processor Ball Description A50 FTM_CH0 X_UART2_RX I O 1 8V AD34 FlexTimer Channel 0 A51 FTM_CH1 X_UART2_TX I O 1 8V AC35 FlexTimer Channel 1 11 3 GPIO The General Purpose Input Output interface pr...

Page 56: ...59 GPIO0_14 X_SPI3_SDO I O 1 8V1 G25 B58 GPIO0_15 X_SPI3_SDI I O 1 8V1 H24 B55 GPIO0_16 X_SPI3_CS0 I O 1 8V1 D26 A53 GPIO0_19 X_MCLK_IN0 I O 1 8V1 L23 A55 GPIO0_20 X_MCLK_OUT0 I O 1 8V1 K24 A60 GPIO0_...

Page 57: ...s LDO4 domain The default voltage level is listed here but always check the actual voltage setting for the applicable SOM configuration Table 50 GPIO2 Accessibility at phyCORE Connector X1 Pin Process...

Page 58: ...DHC1_DATA3 NAND_ALE I O 1 8VJ11 E25 1 The voltage level for these signals is configurable between 1 8V or 3 3V using the PMIC s LDO4 domain The default voltage level is listed here but always check th...

Page 59: ...V AL9 KPP Column 2 D8 KPP0_COL3 X_QSPI0_DATA6 I O 1 8V AJ11 KPP Column 3 D9 KPP0_ROW0 X_QSPI0_DATA7 I O 1 8V AM8 KPP Row 0 C9 KPP0_ROW1 X_QSPI0B_DQS I O 1 8V AL11 KPP Row 1 C6 KPP0_ROW2 X_QSPI0B_SS0_B...

Page 60: ...el Processor Ball Description D14 TAMPER_OUT0 X_CSI_DO0 I O 1 8V AK28 Tamper Out 0 D15 TAMPER_OUT1 X_CSI_DO1 I O 1 8V AL29 Tamper Out 1 D16 TAMPER_OUT2 X_CSI_DO2 I O 1 8V AP30 Tamper Out 2 D17 TAMPER_...

Page 61: ...CORE i MX8X Pin Resources PHYTEC recommends the use of NXP s Pin Muxing Tool The following file is a pin muxing reference for PHYTEC Hardware PCM 065_1488 2_pinmux xlsx The following file is a pin mux...

Page 62: ...1 62 Revision History Table 60 Document Revision History Date Version Number Changes in this Manual 2020 05 20 L 864e A0 Preliminary Release 2021 02 12 L 864e A1 SOM PCB revision from 1488 1 to 1488 2...

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