PCM-065/phyCORE-i.MX8X System on Module
L-864e.A1
© PHYTEC America LLC, 2021
52
9
Display Interfaces
The following subsections detail each of the display interfaces supported on the phyCORE-i.MX8X.
9.1
LVDS/MIPI DSI
The phyCORE-i.MX8X SOM provides two LVDS/MIPI DSI combo display ports with up to four data lanes and
one clock lane to support serialized RGB pixel data transmission. Note that the interface can only be used for
either MIPI DSI or LVDS, not both. The LVDS interface complies with the TIA/EIA 644-A standard. The locations
of the LVDS/MIPI DSI display signals at the phyCORE-Connector are listed in the table below.
Table 41. LVDS/MIPI Connections at the phyCORE-Connector
X1
Pin #
SOM Signal
Type
Level
Processor
Ball
Description
C11
X_MIPI_DSI0_I2C0_SDA
OD-I/O
3.3V
V22
LVDS0/MIPI DSI0 I2C0 Data
C12
X_MIPI_DSI0_I2C0_SCL
OD-O
3.3V
W27
LVDS0/MIPI DSI0 I2C0 Clock
C13
X_MIPI_DSI0_GPIO0_00
I/O
3.3V
AD32
LVDS0/MIPI DSI0 GPIO 0 (the PWM
is also routed through this signal)
C14
X_MIPI_DSI0_GPIO0_01
I/O
3.3V
AE35
LVDS0/MIPI DSI0 GPIO 1
C16
X_MIPI_DSI0_DATA3_N
O
Differential
AJ15
LVDS0/MIPI DSI0 Data 3 Negative
C17
X_MIPI_DSI0_DATA3_P
O
Differential
AK16
LVDS0/MIPI DSI0 Data 3 Positive
C18
X_MIPI_DSI0_DATA1_N
O
Differential
AJ17
LVDS0/MIPI DSI0 Data 1 Negative
C19
X_MIPI_DSI0_DATA1_P
O
Differential
AK18
LVDS0/MIPI DSI0 Data 1 Positive
C21
X_MIPI_DSI0_DATA0_N
O
Differential
AJ21
LVDS0/MIPI DSI0 Data 0 Negative
C22
X_MIPI_DSI0_DATA0_P
O
Differential
AK22
LVDS0/MIPI DSI0 Data 0 Positive
C23
X_MIPI_DSI0_DATA2_N
O
Differential
AJ23
LVDS0/MIPI DSI0 Data 2 Negative
C24
X_MIPI_DSI0_DATA2_P
O
Differential
AK24
LVDS0/MIPI DSI0 Data 2 Positive
C26
X_MIPI_DSI0_CLK_N
O
Differential
AJ19
LVDS0/MIPI DSI0 Clock Negative
C27
X_MIPI_DSI0_CLK_P
O
Differential
AK20
LVDS0/MIPI DSI0 Clock Positive
C28
X_MIPI_DSI1_CLK_N
O
Differential
AM16
LVDS1/MIPI DSI1 Clock Negative
C29
X_MIPI_DSI1_CLK_P
O
Differential
AP16
LVDS1/MIPI DSI1 Clock Positive
C31
X_MIPI_DSI1_DATA2_N
O
Differential
AM14
LVDS1/MIPI DSI1 Data 2 Negative
C32
X_MIPI_DSI1_DATA2_P
O
Differential
AP14
LVDS1/MIPI DSI1 Data 2 Positive
C33
X_MIPI_DSI1_DATA1_N
O
Differential
AN17
LVDS1/MIPI DSI1 Data 1 Negative
C34
X_MIPI_DSI1_DATA1_P
O
Differential
AR17
LVDS1/MIPI DSI1 Data 1 Positive
C36
X_MIPI_DSI1_DATA0_N
O
Differential
AN15
LVDS1/MIPI DSI1 Data 0 Negative
C37
X_MIPI_DSI1_DATA0_P
O
Differential
AR15
LVDS1/MIPI DSI1 Data 0 Positive
C38
X_MIPI_DSI1_DATA3_N
O
Differential
AM18
LVDS1/MIPI DSI1 Data 3 Negative
C39
X_MIPI_DSI1_DATA3_P
O
Differential
AP18
LVDS1/MIPI DSI1 Data 3 Positive
C41
X_MIPI_DSI1_I2C0_SCL
OD-I/O
3.3V
AE33
LVDS1/MIPI DSI1 I2C0 Data
C42
X_MIPI_DSI1_I2C0_SDA
OD-O
3.3V
AC29
LVDS1/MIPI DSI1 I2C0 Clock
C43
X_MIPI_DSI1_GPIO0_00
I/O
3.3V
AD30
LVDS1/MIPI DSI1 GPIO 0 (the PWM
is also routed through this signal)
C44
X_MIPI_DSI1_GPIO0_01
I/O
3.3V
AF34
LVDS1/MIPI DSI1 GPIO 1
