Philips SD-4.00SA CH, Service Manual

Page: 56 / 65

Circuit Descriptions, List of Abbreviations and IC Data EN 56 SD-4.00SA_CH 9.
The SACD DSD/DST decoder Furore 2 uses 1.8V for its core
and analogue portion, and 3.3V for its interface. The on-board
1.8V linear regulator LF18ABDT and 3.3V linear LD1117DT33
are used to generate 1.8V and 3.3V power supply respectively.
The back-end section mainly uses the 1.8V or 2.5V and 3.3V,
which depend on which back-end processor is used. The on-
board linear regulators LF25ABDT or LF18ABDT are used to
generate the 2.5V (or 1.8V) required by the STi55xx.
The front-end section mainly uses the 5V and 12V. An on-
board linear regulator LD1117DT33 can be used to generate
the 3.3V required by the front-end. The 12V is used by the
motor and servo drivers.
Reset Circuit
Figure 9-8 Block diagram of reset circuit
This reset circuit takes care that booting the different devices
on the mono board takes place in the correct order. The correct
reset order is:
1.
The Power On Reset circuit (delay t1) creates a reset
signal 'RESETn' to reset the STi55xx and Furore .
2. In the meantime, the Power On Reset circuit (delay t1)
creates a reset signal 'CLK_STBCTRL', which is inverted
to 'RESETn', to enable the Clock Factory.
3. Then, the Power On Reset circuit (delay t2) generates a
reset signal 'RES_P' to reset the Basic Engine.
4. The STI55xx can now reset the Basic Engine via 'RSTN'.
9.3 Abbreviation List
ADC Analogue to Digital Converter
AM Amplitude Modulation
BE Basic Engine
ComPair Computer aided rePair
CD-DA CD Digital Audio
CS Chip Select
DAC Digital to Analogue Converter
DAIO Digital Audio Input Output
DENC Digital Encoder
DFU Direction For Use: description for the
end user
DNR Dynamic Noise Reduction
DRAM Dynamic RAM
DSD Direct Stream Digital
DSP Digital Signal Processing
DTS Digital Theatre Sound
DVD Digital Versatile Disc
EEPROM Electrically Erasable and
Programmable Read Only Memory
EFM Eight to Fourteen bit Modulation
EMI External Memory Interface (STi55xx)
FFC Flat Foil Cable
FLASH Flash memory
HPF High Pass Filter
HW Hardware
I2C Integrated IC bus (signals at 5V level)
I2S Integrated IC Sound bus (signals at
3.3V level)
IC Integrated Circuit
IF Intermediate Frequency
IRQ Interrupt Request
LLD Loss Less Decoder
LPCM Linear Pulse Code Modulation
LRCLK Left/Right clock
LVTTL Low Voltage Transistor Transistor
Logic (3.3V logic)
MACE Mini All Compact Disc Engine
MPEG Motion Pictures Experts Group
NC Not Connected
NVM Non Volatile Memory: IC containing
TV related data e.g. alignments
OC Open Circuit
OPU Optical Pick-up Unit
PCB Printed Circuit Board (see PWB)
PCM Pulse Code Modulation
PCM_CLK Audio system clock for DAC
PCM_OUTx Audio serial output data
PSU Power Supply Unit
PWB Printed Wiring Board (see PCB)
RAM Random Access Memory
RGB Red, Green and Blue colour space
ROM Read Only Memory
S2B Serial to Basic Engine, communication
bus between host- and servo
processor
SCL Serial Clock I2C
SCLK Audio serial bit clock
SDA Serial Data I2C
SDRAM Synchronous DRAM
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
STBY Standby
SVCD Super Video CD
SW Software
THD Total Harmonic Distortion
TTL Transistor Transistor Logic (5V logic)
uP Microprocessor
VCD Video CD
Y/C Luminance (Y) and Chrominance (C)
signal
YUV Component video
RES_P
CLK_STBCTRL
CL 26532053_018.eps
260402
STi55xx
Power On
Reset
Circuit
Delay 1
Furore 2
Clock Factory
Low Voltage
Detection
4.5V
Low Voltage
Detection
4.5V
Basic Engine
Power On
Reset
Circuit
Delay 2
RSTN
RESETn