Philips SAA7102 Datasheet Download Page 70 | Manualshive

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2004 Mar 01

70

Philips Semiconductors

Product specification

Digital video encoder

SAA7102; SAA7103

handbook, halfpage

MHB912

2.7

µ

H

120 pF

C16

JP11

JP12

FIN

FOUT

C10

390 pF

C13
560 pF

L2

2.7

µ

H

L3

FILTER 1

= byp.

ll act.

AGND

Fig.16 FLTR0, FLTR1 and FLTR2 of Fig.15.

12.1

Analog output voltages

The analog output voltages are dependent on the total
load (typical value 37.5

Ω

), the digital gain parameters and

the I

2

C-bus settings of the DAC reference currents (analog

settings).

The digital output signals in front of the DACs under
nominal (nominal here stands for the settings given in
Tables 54 to 61 for example a standard PAL or NTSC
signal) conditions occupy different conversion ranges, as
indicated in Table 113 for a

100

⁄

100

colour bar signal.

By setting the reference currents of the DACs as shown in
Table 113, standard compliant amplitudes can be
achieved for all signal combinations; it is assumed that in
subaddress 16H, parameter DACF = 0000b, that means
the fine adjustment for all DACs in common is set to 0%.

If S-video output is desired, the adjustment for the C
(chrominance subcarrier) output should be identical to the
one for VBS (luminance plus sync) output.

Table 113 Digital output signals conversion range

SET/OUT

CVBS, SYNC TIP-TO-WHITE VBS, SYNC TIP-TO-WHITE

RGB, BLACK-TO-WHITE

Digital settings

see Tables 54 to 61

see Tables 54 to 61

see Table 49

Digital output

1014

881

876

Analog settings

e.g. B DAC = 1FH

e.g. G DAC = 1BH

e.g. R DAC = G DAC = B DAC = 0BH

Analog output

1.23 V (p-p)

1.00 V (p-p)

0.70 V (p-p)

12.2

Suggestions for a board layout

Use separate ground planes for analog and digital ground.
Connect these planes only at one point directly under the
device, by using a 0

Ω

resistor directly at the supply stage.

Use separate supply lines for the analog and digital supply.
Place the supply decoupling capacitors close to the supply
pins.

Use L

bead

(ferrite coil) in each digital supply line close to

the decoupling capacitors to minimize radiation energy
(EMC).

Place the analog coupling (clamp) capacitors close to the
analog input pins. Place the analog termination resistors
close to the coupling capacitors.

Be careful of hidden layout capacitors around the crystal
application.

Use serial resistors in clock, sync and data lines, to avoid
clock or data reflection effects and to soften data energy.

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Summary of Contents for SAA7102

Page 1: ...DATA SHEET Product specification Supersedes data of 2002 Feb 18 2004 Mar 01 INTEGRATED CIRCUITS SAA7102 SAA7103 Digital video encoder ...

Page 2: ...generator 7 16 I2C bus interface 7 17 Programming the SAA7102 SAA7103 7 18 Input levels and formats 7 19 Bit allocation map 7 20 I2C bus format 7 21 Slave receiver 7 22 Slave transmitter 8 BOUNDARY SCAN TEST 8 1 Initialization of boundary scan circuit 8 2 Device identification codes 9 LIMITING VALUES 10 THERMAL CHARACTERISTICS 11 CHARACTERISTICS 11 1 Teletext timing 12 APPLICATION INFORMATION 12 1...

Page 3: ...ator CBG Optional support of various Vertical Blanking Interval VBI data insertion Macrovision 1 Pay per View copy protection system rev 7 01 and rev 6 1 as option this applies to the SAA7102 only The device is protected by USA patent numbers 4631603 4577216 and 4819098 and other intellectual property rights Use of the Macrovision anti copy process in the device is licensed for non commercial home...

Page 4: ...1 75 mm SOT307 2 SAA7103H SYMBOL PARAMETER MIN TYP MAX UNIT VDDA analog supply voltage 3 15 3 3 3 45 V VDDD digital supply voltage 3 0 3 3 3 6 V IDDA analog supply current 1 110 140 mA IDDD digital supply current 1 70 90 mA Vi input signal voltage levels TTL compatible Vo p p analog CVBS output signal voltage for a 100 100 colour bar at 75 2 Ω load peak to peak value 1 23 V RL load resistance 37 5...

Page 5: ...rce landscape pages to be 5 BLOCK DIAGRAM VERTICAL SCALER AND ANTI FLICKER FILTER FIFO HORIZONTAL SCALER DECIMATOR 4 4 4 to 4 2 2 OR BYPASS TRIPLE DAC BLUE_CB_CVBS GREEN_VBS_CVBS RED_CR_C 30 28 27 HSM_CSYNC 26 VSM 25 VIDEO ENCODER BORDER GENERATOR CURSOR INSERTION RGB TO Y CB CR MATRIX OR BYPASS RGB LUT OR BYPASS I2C BUS CONTROL OSCILLATOR DTO TIMING GENERATOR 13 34 35 23 FSVGC VSVGC XTAL 27 MHz T...

Page 6: ... I pixel clock input looped through PD3 F3 16 I MSB 4 with CB Y CR 4 2 2 see Tables 25 to 30 for pin assignment PD2 H1 17 I MSB 5 with CB Y CR 4 2 2 see Tables 25 to 30 for pin assignment PD1 H2 18 I MSB 6 with CB Y CR 4 2 2 see Tables 25 to 30 for pin assignment PD0 H3 19 I MSB 7 with CB Y CR 4 2 2 see Tables 25 to 30 for pin assignment PIXCLKO G4 20 O pixel clock output to VGC CBO G3 21 O compos...

Page 7: ...ted via 1 kΩ resistor to analog ground do not use capacitor in parallel with 1 kΩ resistor DUMP A7 B7 32 O DAC reference pin connected via 12 Ω resistor to analog ground VSSA1 A8 B8 33 S analog ground 1 XTALO A6 34 O crystal oscillator output XTALI A5 35 I crystal oscillator input VDDA2 B6 D6 36 S analog supply voltage 2 3 3 V for DACs and oscillator TRST A4 37 I test reset input for BST active LO...

Page 8: ...6 7 8 9 10 11 12 13 14 A PD7 PD4 TRST XTALI XTALO DUMP VSSA1 RSET VDDA1 B PD9 PD8 PD5 PD6 TDI VDDA2 DUMP VSSA1 VDDA1 C PD11 PD10 TTX_ SRES TTXRQ_ XCLKO2 VSSD2 BLUE_ CB_ CVBS GREEN_ VBS_ CVBS RED_ CR_ C VDDA1 D TDO RESET TMS VDDD2 VSSD2 VDDA2 VSM HSM_ CSYNC VDDA1 E TCK SCL HSVGC VSSD1 F VSVGCPIXCLKI PD3 VDDD1 G FSVGC SDA CBO PIXCLKO H PD2 PD1 PD0 J K L M N P ...

Page 9: ...gewidth SAA7102H SAA7103H MHB908 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 PD7 PD6 PD5 PD4 V DDD2 V SSD2 TDI TRST V DDA2 XTALI XTALO SDA FSVGC VSVGC PIXCLKI PD3 PD2 PD1 PD0 PIXCLKO CBO HSVGC PD8 PD9 PD10 PD11 TMS TDO TCK VSSD1 VDDD1 SCL VSSA1 DUMP RSET BLUE_CB_CVBS VDDA1 GREEN_VBS_CVBS RED_CR_C HSM_CSYNC VSM TTXRQ_XCL...

Page 10: ... crystal stable clock rate of 13 5 MHz independent of the actual pixel clock used at the input side corresponding to an internal 4 2 2 bandwidth in the luminance colour difference domain Luminance and chrominance signals are filtered in accordance with the standard requirements of RS 170 A and ITU R BT 470 3 For ease of analog post filtering the signals are twice oversampled to 27 MHz before digit...

Page 11: ... line until the middle of the line immediately preceding the first active line The first 3 bytes represent the first RGB LUT data and so on 7 4 Cursor insertion A 32 32 dots cursor can be overlaid as an option the bit map of the cursor can be uploaded by an I2C bus write access to specific registers or in the pixel data input through the PD port In the latter case the 256 bytes defining the cursor...

Page 12: ...ur The phase resolution of the circuit is 12 bits giving a maximum offset of 0 2 after 800 input pixels Small FIFOs rearrange a 4 2 2 data stream at the scaler output 7 7 Vertical scaler and anti flicker filter The functions scaling Anti Flicker Filter AFF and re interlacing are implemented in the vertical scaler Besides the entire input frame it receives the first and last lines of the border to ...

Page 13: ...itable for use as CVBS or separate Y and C signals Input to the encoder at 27 MHz clock e g DVD is either originated from computer graphics at pixel clock fed through the FIFO and border generator or a ITU R BT 656 style signal Luminance is modified in gain and in offset the offset is programmable in a certain range to enable different black level set ups A blanking level can be set after insertio...

Page 14: ...ing for colour difference signals is performed The transfer curves of luminance and colour difference components of RGB are illustrated in Figs 8 and 9 7 14 Triple DAC Both Y and C signals are converted from digital to analog in a 10 bit resolution at the output of the video encoder Y and C signals are also combined into a 10 bit CVBS signal The CVBS output signal occurs with the same processing d...

Page 15: ...l timings do not change in this case so the first active line can be number 2 counted from 0 7 16 I2C bus interface The I2C bus interface is a standard slave transceiver supporting 7 bit slave addresses and 400 kbits s guaranteed transfer rate It uses 8 bit subaddressing with an auto increment function All registers are write and read except two read only status bytes The register bit map consists...

Page 16: ...IP defines the anti flicker function 0 means maximum flicker reduction but minimum vertical bandwidth 4095 gives no flicker reduction and maximum bandwidth When YINC 0 it sets the scaler to scaling factor 1 The initial weighting factors must not be set to 0 in this case YIWGTE may go negative In this event YINC should be added and YOFSE incremented This can be repeated as often as necessary to mak...

Page 17: ...1099 2163 0 56 56 3128 1080 212 0 33 245 1851099 2163 0 60 60 3128 1080 212 2 35 247 1851099 2163 0 63 63 3128 1080 212 4 37 249 1851099 2163 0 67 67 3128 1080 214 4 28 242 1836201 2181 0 50 50 3138 1090 214 2 30 244 1836201 2181 0 54 54 3138 1090 214 0 32 246 1836201 2181 0 57 57 3138 1090 214 2 34 248 1836201 2181 0 61 61 3138 1090 214 4 36 250 1836201 2181 0 65 65 3138 1090 216 4 27 243 1817578...

Page 18: ...5 1790 61 61 3683 611 214 4 36 250 1836201 3135 1790 65 65 3683 611 216 4 27 243 1817578 3145 1750 48 48 3698 626 216 2 29 245 1817578 3145 1750 51 51 3698 626 216 0 31 247 1817578 3145 1750 55 55 3698 626 216 2 33 249 1817578 3145 1750 59 59 3698 626 216 4 35 251 1817578 3145 1750 63 63 3698 626 218 4 26 244 1802680 3155 1720 45 45 3714 642 218 2 28 246 1802680 3155 1720 49 49 3714 642 218 0 30 2...

Page 19: ...8 3580 61 61 4091 253 214 4 36 250 1836201 4088 3580 65 65 4091 253 216 4 27 243 1817578 4093 3510 48 48 4091 288 216 2 29 245 1817578 4093 3510 52 52 4091 288 216 0 31 247 1817578 4093 3510 55 55 4091 288 216 2 33 249 1817578 4093 3510 59 59 4091 288 216 4 35 251 1817578 4093 3510 63 63 4091 288 218 4 26 244 1802680 4092 3445 46 46 4092 322 218 2 28 246 1802680 4092 3445 49 49 4092 322 218 0 30 2...

Page 20: ...248 2201206 1819 0 73 73 2957 909 214 4 36 250 2201206 1819 0 78 78 2957 909 216 4 27 243 2178859 1836 0 57 57 2965 917 216 2 29 245 2178859 1836 0 61 61 2965 917 216 0 31 247 2178859 1836 0 66 66 2965 917 216 2 33 249 2178859 1836 0 70 70 2965 917 216 4 35 251 2178859 1836 0 75 75 2965 917 218 4 26 244 2160236 1853 0 54 54 2974 926 218 2 28 246 2160236 1853 0 59 59 2974 926 218 0 30 248 2160236 1...

Page 21: ...30 2048 74 74 3412 340 214 4 36 250 2201206 2730 2048 78 78 3412 340 216 4 27 243 2178859 2756 2048 57 57 3424 352 216 2 29 245 2178859 2756 2048 62 62 3424 352 216 0 31 247 2178859 2756 2048 66 66 3424 352 216 2 33 249 2178859 2756 2048 71 71 3424 352 216 4 35 251 2178859 2756 2048 75 75 3424 352 218 4 26 244 2160236 2781 2048 55 55 3437 365 218 2 28 246 2160236 2781 2048 59 59 3437 365 218 0 30 ...

Page 22: ...5 74 75 3866 3413 214 4 36 250 2201206 3639 4095 78 79 3866 3413 216 4 27 243 2178859 3675 4095 57 58 3883 3464 216 2 29 245 2178859 3675 4095 62 63 3883 3464 216 0 31 247 2178859 3675 4095 66 67 3883 3464 216 2 33 249 2178859 3675 4095 71 72 3883 3464 216 4 35 251 2178859 3675 4095 75 76 3883 3464 218 4 26 244 2160236 3709 4095 55 56 3900 3515 218 2 28 246 2160236 3709 4095 59 60 3900 3515 218 0 ...

Page 23: ...54 1457 0 92 92 2776 728 214 4 36 250 3518354 1457 0 98 98 2776 728 216 4 27 243 3484982 1470 0 72 72 2782 734 216 2 29 245 3484982 1470 0 77 77 2782 734 216 0 31 247 3484982 1470 0 82 82 2782 734 216 2 33 249 3484982 1470 0 88 88 2782 734 216 4 35 251 3484982 1470 0 94 94 2782 734 218 4 26 244 3451610 1484 0 68 68 2789 741 218 2 28 246 3451610 1484 0 73 73 2789 741 218 0 30 248 3451610 1484 0 79 ...

Page 24: ...8 92 92 3140 68 214 4 36 250 3518354 2185 2048 98 98 3140 68 216 4 27 243 3484982 2205 2048 72 72 3150 78 216 2 29 245 3484982 2205 2048 77 77 3150 78 216 0 31 247 3484982 2205 2048 83 83 3150 78 216 2 33 249 3484982 2205 2048 89 89 3150 78 216 4 35 251 3484982 2205 2048 94 94 3150 78 218 4 26 244 3451610 2226 2048 68 68 3160 88 218 2 28 246 3451610 2226 2048 74 74 3160 88 218 0 30 248 3451610 222...

Page 25: ... 2323 214 4 36 250 3518354 2912 4095 98 99 3504 2323 216 4 27 243 3484982 2941 4095 72 73 3517 2364 216 2 29 245 3484982 2941 4095 78 79 3517 2364 216 0 31 247 3484982 2941 4095 83 84 3517 2364 216 2 33 249 3484982 2941 4095 89 90 3517 2364 216 4 35 251 3484982 2941 4095 94 95 3517 2364 218 4 26 244 3451610 2969 4095 69 70 3531 2405 218 2 28 246 3451610 2969 4095 74 75 3531 2405 218 0 30 248 34516...

Page 26: ...516163 2623 0 60 60 3357 1309 257 4 42 299 1516163 2623 0 63 63 3357 1309 259 4 33 292 1506842 2641 0 49 49 3367 1319 259 2 35 294 1506842 2641 0 52 52 3367 1319 259 0 37 296 1506842 2641 0 55 55 3367 1319 259 2 39 298 1506842 2641 0 58 58 3367 1319 259 4 41 300 1506842 2641 0 61 61 3367 1319 261 4 32 293 1494414 2661 0 47 47 3377 1329 261 2 34 295 1494414 2661 0 50 50 3377 1329 261 0 36 297 14944...

Page 27: ...0 1150 60 60 4012 940 257 4 42 299 1516163 3360 1150 63 63 4012 940 259 4 33 292 1506842 3362 1120 49 49 4070 998 259 2 35 294 1506842 3362 1120 52 52 4070 998 259 0 37 296 1506842 3362 1120 55 55 4070 998 259 2 39 298 1506842 3362 1120 58 58 4070 998 259 4 41 300 1506842 3362 1120 61 61 4070 998 261 4 32 293 1494414 3378 1100 47 47 4042 970 261 2 34 295 1494414 3378 1100 50 50 4042 970 261 0 36 2...

Page 28: ... 2300 60 60 4092 894 257 4 42 299 1516163 4095 2300 63 63 4092 894 259 4 33 292 1506842 4093 2250 49 49 4092 919 259 2 35 294 1506842 4093 2250 52 52 4092 919 259 0 37 296 1506842 4093 2250 55 55 4092 919 259 2 39 298 1506842 4091 2250 58 58 4092 919 259 4 42 301 1506842 4091 2250 63 63 4092 919 261 4 32 293 1494414 4094 2200 47 47 4092 944 261 2 34 295 1494414 4094 2200 50 50 4092 944 261 0 36 29...

Page 29: ...820638 2185 0 72 72 3139 1091 257 4 42 299 1820638 2185 0 76 76 3139 1091 259 4 33 292 1805104 2202 0 58 58 3148 1100 259 2 35 294 1805104 2202 0 62 62 3148 1100 259 0 37 296 1805104 2202 0 66 66 3148 1100 259 2 39 298 1805104 2204 0 70 70 3148 1100 259 4 41 300 1805104 2202 0 73 73 3148 1100 261 4 32 293 1792676 2219 0 56 56 3156 1108 261 2 34 295 1792676 2219 0 60 60 3156 1108 261 0 36 297 17926...

Page 30: ...7 2048 72 72 3686 614 257 4 42 299 1820638 3277 2048 76 76 3686 614 259 4 33 292 1805104 3305 2048 59 59 3698 626 259 2 35 294 1805104 3305 2048 63 63 3698 626 259 0 37 296 1805104 3305 2048 66 66 3698 626 259 2 39 298 1805104 3305 2048 70 70 3698 626 259 4 41 300 1805104 3305 2048 74 74 3698 626 261 4 32 293 1792676 3328 2048 57 57 3711 639 261 2 34 295 1792676 3328 2048 60 60 3711 639 261 0 36 2...

Page 31: ... 3570 73 73 4091 258 257 4 42 299 1820638 4090 3570 76 76 4091 258 259 4 33 292 1805104 4092 3510 59 59 4091 288 259 2 35 294 1805104 4092 3510 63 63 4091 288 259 0 37 296 1805104 4092 3510 66 66 4091 288 259 2 39 298 1805104 4092 3510 70 70 4091 288 259 4 41 300 1805104 4092 3510 74 74 4091 288 261 4 32 293 1792676 4088 3450 57 57 4091 318 261 2 34 295 1792676 4088 3450 60 60 4091 318 261 0 36 29...

Page 32: ...33 1749 0 91 91 2922 874 257 4 42 299 2911033 1749 0 95 95 2922 874 259 4 33 292 2887172 1763 0 73 73 2929 881 259 2 35 294 2887172 1763 0 78 78 2929 881 259 0 37 296 2887172 1763 0 83 83 2929 881 259 2 39 298 2887172 1763 0 87 87 2929 881 259 4 41 300 2887172 1763 0 92 92 2929 881 261 4 32 293 2863311 1778 0 71 71 2935 887 261 2 34 295 2863311 1778 0 75 75 2935 887 261 0 36 297 2863311 1778 0 80 ...

Page 33: ...1 3359 287 257 4 42 299 2911033 2625 2048 96 96 3359 287 259 4 33 292 2887172 2645 2048 74 74 3369 297 259 2 35 294 2887172 2645 2048 79 79 3369 297 259 0 37 296 2887172 2645 2048 83 83 3369 297 259 2 39 298 2887172 2645 2048 88 88 3369 297 259 4 41 300 2887172 2645 2048 92 92 3369 297 261 4 32 293 2863311 2666 2048 71 71 3379 307 261 2 34 295 2863311 2666 2048 75 75 3379 307 261 0 36 297 2863311 ...

Page 34: ... 3202 257 4 42 299 2911033 3500 4095 96 97 3796 3202 259 4 33 292 2887172 3527 4095 74 75 3810 3242 259 2 35 294 2887172 3527 4095 79 80 3810 3242 259 0 37 296 2887172 3527 4095 83 84 3810 3242 259 2 39 298 2887172 3527 4095 88 89 3810 3242 259 4 41 300 2887172 3527 4095 93 94 3810 3242 261 4 32 293 2863311 3555 4095 71 72 3823 3284 261 2 34 295 2863311 3555 4095 76 77 3823 3284 261 0 36 297 28633...

Page 35: ... CR PIN FALLING CLOCK EDGE RISING CLOCK EDGE PD11 G3 Y3 R7 CR7 PD10 G2 Y2 R6 CR6 PD9 G1 Y1 R5 CR5 PD8 G0 Y0 R4 CR4 PD7 B7 CB7 R3 CR3 PD6 B6 CB6 R2 CR2 PD5 B5 CB5 R1 CR1 PD4 B4 CB4 R0 CR0 PD3 B3 CB3 G7 Y7 PD2 B2 CB2 G6 Y6 PD1 B1 CB1 G5 Y5 PD0 B0 CB0 G4 Y4 5 5 5 BIT 4 4 4 NON INTERLACED RGB PIN FALLING CLOCK EDGE RISING CLOCK EDGE PD7 G2 X PD6 G1 R4 PD5 G0 R3 PD4 B4 R2 PD3 B3 R1 PD2 B2 R0 PD1 B1 G4 ...

Page 36: ...5 CB5 0 Y5 0 CR5 0 Y5 1 PD4 CB4 0 Y4 0 CR4 0 Y4 1 PD3 CB3 0 Y3 0 CR3 0 Y3 1 PD2 CB2 0 Y2 0 CR2 0 Y2 1 PD1 CB1 0 Y1 0 CR1 0 Y1 1 PD0 CB0 0 Y0 0 CR0 0 Y0 1 8 BIT NON INTERLACED INDEX COLOUR PIN FALLING CLOCK EDGE RISING CLOCK EDGE PD11 X X PD10 X X PD9 X X PD8 X X PD7 INDEX7 X PD6 INDEX6 X PD5 INDEX5 X PD4 INDEX4 X PD3 INDEX3 X PD2 INDEX2 X PD1 INDEX1 X PD0 INDEX0 X 8 8 8 BIT 4 4 4 NON INTERLACED RG...

Page 37: ...P Chip ID 02B or 03B read only 1C CID7 CID6 CID5 CID4 CID3 CID2 CID1 CID0 Wide screen signal 26 WSS7 WSS6 WSS5 WSS4 WSS3 WSS2 WSS1 WSS0 Wide screen signal 27 WSSON 1 WSS13 WSS12 WSS11 WSS10 WSS9 WSS8 Real time control burst start 28 1 1 BS5 BS4 BS3 BS2 BS1 BS0 Sync reset enable burst end 29 SRES 1 BE5 BE4 BE3 BE2 BE1 BE0 Copy generation 0 2A CG07 CG06 CG05 CG04 CG03 CG02 CG01 CG00 Copy generation ...

Page 38: ...1O03 L21O02 L21O01 L21O00 Line 21 odd 1 68 L21O17 L21O16 L21O15 L21O14 L21O13 L21O12 L21O11 L21O10 Line 21 even 0 69 L21E07 L21E06 L21E05 L21E04 L21E03 L21E02 L21E01 L21E00 Line 21 even 1 6A L21E17 L21E16 L21E15 L21E14 L21E13 L21E12 L21E11 L21E10 Null 6B 1 1 1 1 1 1 1 1 Trigger control 6C HTRIG7 HTRIG6 HTRIG5 HTRIG4 HTRIG3 HTRIG2 HTRIG1 HTRIG0 Trigger control 6D HTRIG10 HTRIG9 HTRIG8 VTRIG4 VTRIG3...

Page 39: ... XOFS4 XOFS3 XOFS2 XOFS1 XOFS0 Pixel number 91 XPIX7 XPIX6 XPIX5 XPIX4 XPIX3 XPIX2 XPIX1 XPIX0 Vertical offset odd 92 YOFSO7 YOFSO6 YOFSO5 YOFSO4 YOFSO3 YOFSO2 YOFSO1 YOFSO0 Vertical offset even 93 YOFSE7 YOFSE6 YOFSE5 YOFSE4 YOFSE3 YOFSE2 YOFSE1 YOFSE0 MSBs 94 YOFSE9 YOFSE8 YOFSO9 YOFSO8 XPIX9 XPIX8 XOFS9 XOFS8 Line number 95 YPIX7 YPIX6 YPIX5 YPIX4 YPIX3 YPIX2 YPIX1 YPIX0 Scaler CTRL MCB YPIX 96...

Page 40: ... 1 G F1 CC1G7 CC1G6 CC1G5 CC1G4 CC1G3 CC1G2 CC1G1 CC1G0 Cursor colour 1 B F2 CC1B7 CC1B6 CC1B5 CC1B4 CC1B3 CC1B2 CC1B1 CC1B0 Cursor colour 2 R F3 CC2R7 CC2R6 CC2R5 CC2R4 CC2R3 CC2R2 CC2R1 CC2R0 Cursor colour 2 G F4 CC2G7 CC2G6 CC2G5 CC2G4 CC2G3 CC2G2 CC2G1 CC2G0 Cursor colour 2 B F5 CC2B7 CC2B6 CC2B5 CC2B4 CC2B3 CC2B2 CC2B1 CC2B0 Auxiliary cursor colour R F6 AUXR7 AUXR6 AUXR5 AUXR4 AUXR3 AUXR2 AUX...

Page 41: ...rement of the subaddress is performed 7 21 Slave receiver Table 39 Subaddress 16H S 1 0 0 0 1 0 0 0 A SUBADDRESS A DATA 0 A DATA n A P S 1 0 0 0 1 0 0 0 A FEH A RAM ADDRESS A DATA 0 A DATA n A P S 1 0 0 0 1 0 0 0 A FFH A RAM ADDRESS A DATA 0R A DATA 0G A DATA 0B A P S 1 0 0 0 1 0 0 0 A SUBADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am DATA n Am P S 1 0 0 0 1 0 0 0 A FEH or FFH A RAM ADDRESS A Sr 1 0 0 0...

Page 42: ...ED DAC default after reset is 1BH for output of C signal 00000b 0 585 V to 11111b 1 240 V at 37 5 Ω nominal for full scale conversion GDACC output level coarse adjustment for GREEN DAC default after reset is 1BH for output of VBS signal 00000b 0 585 V to 11111b 1 240 V at 37 5 Ω nominal for full scale conversion BDACC output level coarse adjustment for BLUE DAC default after reset is 1FH for outpu...

Page 43: ... check comparator at DAC on pin BLUE_CB_CVBS is inactive output is not loaded DATA BYTE LOGIC LEVEL DESCRIPTION WSS wide screen signalling bits 3 to 0 aspect ratio 7 to 4 enhanced services 10 to 8 subtitles 13 to 11 reserved WSSON 0 wide screen signalling output is disabled default after reset 1 wide screen signalling output is enabled DATA BYTE LOGIC LEVEL DESCRIPTION REMARKS BS starting point of...

Page 44: ... VBS signal default after reset 1 pin GREEN_VBS_CVBS provides a CVBS signal CVBSEN0 0 pin BLUE_CB_CVBS provides a component BLUE B or colour difference BLUE CB signal 1 pin BLUE_CB_CVBS provides a CVBS signal default after reset CEN 0 pin RED_CR_C provides a component RED R or colour difference RED CR signal 1 pin RED_CR_C provides a chrominance signal C as modulated subcarrier for S video default...

Page 45: ...ht binary from PD input port default after reset UV2C 0 input colour difference data is twos complement from PD input port 1 input colour difference data is straight binary from PD input port default after reset DATA BYTE LOGIC LEVEL DESCRIPTION VPSEN 0 video programming system data insertion is disabled default after reset 1 video programming system data insertion in line 16 is enabled EDGE2 0 in...

Page 46: ...er of U contribution 0 GAINU 118 76H output subcarrier of U contribution nominal white to black 100 IRE GAINU 2 05 nominal to 2 04 nominal GAINU 0 output subcarrier of U contribution 0 GAINU 125 7DH output subcarrier of U contribution nominal DATA BYTE DESCRIPTION CONDITIONS REMARKS GAINV variable gain for CR signal input representation in accordance with ITU R BT 601 white to black 92 5 IRE GAINV...

Page 47: ...n for overall transfer characteristic of luminance see Fig 6 0 1 cross colour reduction 1 active for overall transfer characteristic see Fig 6 1 0 cross colour reduction 2 active for overall transfer characteristic see Fig 6 1 1 cross colour reduction 3 active for overall transfer characteristic see Fig 6 DATA BYTE LOGIC LEVEL DESCRIPTION DOWND 0 digital core in normal operational mode default aft...

Page 48: ...ack 100 IRE burst 43 IRE PAL encoding recommended value BSTA 47 2FH default after reset BSTA 0 to 3 02 nominal DATA BYTE DESCRIPTION CONDITIONS REMARKS FSC0 to FSC3 ffsc subcarrier frequency in multiples of line frequency fllc clock frequency in multiples of line frequency note 1 FSC3 most significant byte FSC0 least significant byte DATA BYTE DESCRIPTION REMARKS L21O0 first byte of captioning dat...

Page 49: ...vel PHRES selects the phase reset mode of the colour subcarrier generator see Table 67 LDEL selects the delay on luminance path with reference to chrominance path see Table 68 FLC field length control see Table 69 DATA BYTE DESCRIPTION PHRES1 PHRES0 0 0 no subcarrier reset 0 1 subcarrier reset every two lines 1 0 subcarrier reset every eight fields 1 1 subcarrier reset every four fields DATA BYTE ...

Page 50: ...1 enables encoding in both fields DATA BYTE DESCRIPTION ADWHS active display window horizontal start defines the start of the active TV display portion after the border colour values above 1715 FISE 1 or 1727 FISE 0 are not allowed ADWHE active display window horizontal end defines the end of the active TV display portion before the border colour values above 1715 FISE 1 or 1727 FISE 0 are not all...

Page 51: ...s default after reset if strapped to PAL TTXEVS 05H is default after reset if strapped to NTSC line TTXEVS 4 for M systems line TTXEVS 1 for other systems TTXEVE last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 CLK2EN 0 in even field TTXEVE 16H is default after reset if strapped to PAL TTXEVE 10H is default after reset if strapped to NTSC line TTXEVE 3 for M systems line TTXEVE for othe...

Page 52: ...irection defines half the number of active pixels per input line identical to the length of CBO pulses DATA BYTE DESCRIPTION YOFSO vertical offset in odd field defines in the odd field the number of lines from VSVGC to first line with active CBO if no LUT data is requested the first active CBO will be output at YOFSO 2 usually YOFSO YOFSE with the exception of extreme vertical downscaling and inte...

Page 53: ...d 128 PIXCLKs in advance adapted to a late HSVGC in slave mode DATA BYTE LOGIC LEVEL DESCRIPTION HFS 0 horizontal sync is directly derived from input signal slave mode at pin HSVGC 1 horizontal sync is derived from a frame sync signal slave mode at pin FSVGC only if EFS is set HIGH VFS 0 vertical sync field sync is directly derived from input signal slave mode at pin VSVGC 1 vertical sync field sy...

Page 54: ...ge of the input signal is used in slave mode DATA BYTE DESCRIPTION HLEN horizontal length DATA BYTE DESCRIPTION IDEL input delay defines the distance in PIXCLKs between the active edge of CBO and the first received valid pixel DATA BYTE DESCRIPTION XINC incremental fraction of the horizontal scaling engine DATA BYTE DESCRIPTION YINC incremental fraction of the vertical scaling engine DATA BYTE DES...

Page 55: ...off DATA BYTE LOGIC LEVEL DESCRIPTION BLEN 0 no internal blanking for non interlaced graphics in bypass mode default after reset 1 forced internal blanking for non interlaced graphics in bypass mode DATA BYTE DESCRIPTION BCY BCU and BCV luminance and colour difference portion of border colour in underscan area DATA BYTE DESCRIPTION CC1R CC1G and CC1B RED GREEN and BLUE portion of first cursor colo...

Page 56: ... interlaced RGB 3 input format is 8 8 8 bit 4 2 2 non interlaced CB Y CR 4 input format is 8 8 8 bit 4 2 2 interlaced CB Y CR ITU R BT 656 27 MHz clock in subaddresses 91H and 94H set XPIX number of active pixels line 5 input format is 8 bit non interlaced index colour 6 input format is 8 8 8 bit 4 4 4 non interlaced RGB or CB Y CR special bit ordering MATOFF 0 RGB to CR Y CB matrix is active 1 RG...

Page 57: ...bytes of the odd field have been encoded 0 the bit is reset after information has been written to the subaddresses 67H and 68H it is set immediately after the data has been encoded CCRDE 1 Closed Caption bytes of the even field have been encoded 0 the bit is reset after information has been written to the subaddresses 69H and 6AH it is set immediately after the data has been encoded FSEQ 1 during ...

Page 58: ...A7103 handbook full pagewidth 6 8 10 12 14 6 0 0 2 4 MBE737 6 12 18 30 24 36 42 54 48 f MHz Gv dB 1 2 Fig 4 Chrominance transfer characteristic 1 1 SCBW 1 2 SCBW 0 handbook halfpage 0 0 4 0 8 1 6 2 0 4 6 2 MBE735 1 2 f MHz Gv dB 1 2 Fig 5 Chrominance transfer characteristic 2 1 SCBW 1 2 SCBW 0 ...

Page 59: ...8 10 12 14 6 0 0 2 4 MGD672 6 12 18 30 24 36 42 54 48 f MHz Gv dB Fig 6 Luminance transfer characteristic 1 excluding scaler 1 CCRS1 0 CCRS0 1 2 CCRS1 1 CCRS0 0 3 CCRS1 1 CCRS0 1 4 CCRS1 0 CCRS0 0 handbook halfpage 0 2 1 6 1 0 1 2 3 4 5 MBE736 4 f MHz Gv dB Fig 7 Luminance transfer characteristic 2 excluding scaler 1 CCRS1 0 CCRS0 0 ...

Page 60: ...ull pagewidth 6 8 10 12 14 6 0 0 2 4 MGB708 6 12 18 30 24 36 42 54 48 f MHz Gv dB Fig 8 Luminance transfer characteristic in RGB excluding scaler handbook full pagewidth 6 8 10 12 14 6 0 0 2 4 MGB706 6 12 18 30 24 36 42 54 48 f MHz Gv dB Fig 9 Colour difference transfer characteristic in RGB excluding scaler ...

Page 61: ...in external test mode IDCODE This optional instruction will provide information on the components manufacturer part number and version number INTEST This optional instruction allows testing of the internal logic no support for customer available USER1 This private instruction allows testing by the manufacturer no support for customer available 8 1 Initialization of boundary scan circuit The Test A...

Page 62: ...010 4 bit version code 16 bit part number 11 bit manufacturer identification TDI TDO MHB909 31 MSB LSB 28 27 12 11 1 0 1 handbook full pagewidth 00000010101 0111000100000011 0010 4 bit version code 16 bit part number 11 bit manufacturer identification TDI TDO MHB910 31 MSB LSB 28 27 12 11 1 0 1 Fig 10 32 bits of identification code b SAA7103 a SAA7102 ...

Page 63: ...round layer four layer board second layer can also reduce the effective Rth j a Please do not use any solder stop varnish under the chip In addition the usage of soldering glue with a high thermal conductance after curing is recommended SYMBOL PARAMETER CONDITIONS MIN MAX UNIT VDDD digital supply voltage 0 5 4 6 V VDDA analog supply voltage 0 5 4 6 V Vi A input voltage at analog inputs 0 5 4 6 V V...

Page 64: ... pF data 8 pF I Os at high impedance 8 pF Outputs all digital output pins except pin SDA VOL LOW level output voltage IOL 2 mA 0 4 V VOH HIGH level output voltage IOH 2 mA 2 4 V I2C bus pins SDA and SCL VIL LOW level input voltage 0 5 0 3VDDD V VIH HIGH level input voltage 0 7VDDD VDDD 0 3 V Ii input current Vi LOW or HIGH 10 10 µA VOL LOW level output voltage pin SDA IOL 3 mA 0 4 V Io output curr...

Page 65: ...2 1 5 1 8 fF C0 parallel capacitance typical 2 8 3 5 4 2 pF Data and reference signal output timing Co L output load capacitance 8 40 pF to h output hold time 2 ns to d output delay time 16 ns CVBS and RGB outputs Vo CVBS p p output voltage CVBS peak to peak value see Table 113 1 23 V Vo VBS p p output voltage VBS S video peak to peak value see Table 113 1 0 V Vo C p p output voltage C S video pea...

Page 66: ...pagewidth PIXCLKO PIXCLKI PDn any output td CLKD tHIGH tf tr 2 4 V 1 5 V 0 4 V tHD DAT tHD DAT to h to d tSU DAT tSU DAT TPIXCLK MHB904 2 0 V 1 5 V 0 8 V 2 4 V 0 4 V 2 0 V 0 8 V Fig 11 Input output timing specification handbook full pagewidth HSVGC PD CBO XOFS IDEL XPIX HLEN MHB905 Fig 12 Horizontal input timing ...

Page 67: ...2004 Mar 01 67 Philips Semiconductors Product specification Digital video encoder SAA7102 SAA7103 handbook full pagewidth HSVGC VSVGC CBO YOFS YPIX MHB906 Fig 13 Vertical input timing ...

Page 68: ...TX data is always inserted at the correct position after the leading edge of the outgoing horizontal synchronization pulse Time ti TTXW is the internally used insertion window for TTX data it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6 9375 Mbits s PAL 296 teletext bits at a text data rate of 5 7272 Mbits s world standard TTX or 288 teletext bits at a ...

Page 69: ...3 2 1 PD11 PD10 PD9 PD8 PD3 PD2 PD1 PD0 PD7 PD6 PD5 PD4 PD11 PD10 PD9 PD8 VDDA3_2 VDDA3_1 VDD3_2 VDD3_1 V DDD2 V DDD1 V DDA2 V DDA1 TMS TDI TDO BST0 BST1 BST2 TCK TRST SDA SCL HSVGC HSVGC 34 35 XTALO XTALI 14 VSVGC VSVGC 13 FSVGC FSVGC 21 CBO TP5 HSVGC TP4 CBO TP3 XCLKO2 CBO 23 TTX_SRES TTX_SRES 24 TTXRQ_XCLKO2 TTXRQ_XCLKO2 V SSD2 V SSD1 DUMP RSET PIXCLKI PIXCLKO RESET V SSA1 AGND DGND DGND 10 40 ...

Page 70: ...justment for the C chrominance subcarrier output should be identical to the one for VBS luminance plus sync output Table 113 Digital output signals conversion range SET OUT CVBS SYNC TIP TO WHITE VBS SYNC TIP TO WHITE RGB BLACK TO WHITE Digital settings see Tables 54 to 61 see Tables 54 to 61 see Table 49 Digital output 1014 881 876 Analog settings e g B DAC 1FH e g G DAC 1BH e g R DAC G DAC B DAC...

Page 71: ...JEITA mm 0 5 0 3 1 75 15 2 14 8 D1 13 7 13 0 13 7 13 0 e1 13 e2 13 1 25 1 05 y1 0 6 0 4 0 1 0 15 0 35 DIMENSIONS mm are the original dimensions SOT472 1 144E MS 034 15 2 14 8 E w 0 3 v 0 5 10 mm scale SOT472 1 BGA156 plastic ball grid array package 156 balls body 15 x 15 x 1 15 mm A max y1 C C E1 D D1 X E 1 A B C D E F G H J K L M N P 2 3 4 5 6 7 8 9 10 11 12 13 14 B A ball A1 index area e e e1 b ...

Page 72: ... 9 12 3 1 2 0 8 10 0 o o 0 15 0 1 0 15 DIMENSIONS mm are the original dimensions Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included 0 95 0 55 SOT307 2 97 08 01 03 02 25 D 1 1 1 10 1 9 9 HD 12 9 12 3 E Z 1 2 0 8 D e E B 11 c E H D ZD A ZE e v M A X 1 44 34 33 23 22 12 y θ A1 A Lp detail X L A 3 A2 pin 1 index D H v M B bp bp w M w M 0 2 5 5 mm scale QFP44 plastic quad ...

Page 73: ...ackage either below the seating plane or not more than 2 mm above it If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds If the bit temperature is between 300 and 400 C contact may be up to 5 seconds 14 3 Surface mount packages 14 3 1 REFLOW SOLDERING Reflow soldering requires solder paste a suspension of fine solder particles flux and bind...

Page 74: ...e to the transport direction of the printed circuit board The footprint must incorporate solder thieves downstream and at the side corners During placement and before soldering the package must be fixed with a droplet of adhesive The adhesive can be applied by screen printing pin transfer or syringe dispensing The package can be soldered after the adhesive is cured Typical dwell time of the leads ...

Page 75: ...inted circuit board and the heatsink On versions with the heatsink on the top side the solder might be deposited on the heatsink surface 7 If wave soldering is considered then the package must be placed at a 45 angle to the solder wave direction The package footprint must incorporate solder thieves downstream and at the side corners 8 Wave soldering is suitable for LQFP QFP and TQFP packages with ...

Page 76: ...tion Limiting values given are in accordance with the Absolute Maximum Rating System IEC 60134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for exte...

Page 77: ...3 18 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips This specification can be ordered using the code 9398 393 40011 ...

Page 78: ...ability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Philips Semiconductors a worldwide company Contact information For additional information please visit http www semiconductors philips com Fax 31 40 27 24825 For sales offices addresses send e mail to sal...

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