2004 Mar 01
13
Philips Semiconductors
Product specification
Digital video encoder
SAA7102; SAA7103
7.8
FIFO
The FIFO acts as a buffer to translate from the PIXCLK
clock domain to the XTAL clock domain. The write clock is
PIXCLK and the read clock is XTAL. An underflow or
overflow condition can be detected via the I
2
C-bus read
access.
In order to avoid underflows and overflows, it is essential
that the frequency of the synthesized PIXCLK matches to
the input graphics resolution and the desired scaling
factor. It is suggested to refer to Tables 6 to 23 for some
representative combinations.
7.9
Border generator
When the graphics picture is to be displayed as interlaced
PAL, NTSC, S-video or RGB on a TV screen, it is desired
in many cases not to lose picture information due to the
inherent overscanning of a TV set. The desired amount of
underscan area, which is achieved through appropriate
scaling in the vertical and horizontal direction, can be filled
in the border generator with an arbitrary true colour tint.
7.10
Oscillator and Discrete Time Oscillator (DTO)
The master clock generation is realized as a 27 MHz
crystal oscillator, which can operate with either a
fundamental wave crystal or a 3rd-harmonic crystal.
The crystal clock supplies the DTO of the pixel clock
synthesizer, the video encoder and the I
2
C-bus control
block. It also usually supplies the triple DAC, with the
exception of the auxiliary VGA mode, where the triple DAC
is clocked by the pixel clock (PIXCLK).
The DTO can be programmed to synthesize all relevant
pixel clock frequencies between circa 18 and 44 MHz.
7.11
Low-pass Clock Generation Circuit (CGC)
This block reduces the phase jitter of the synthesized pixel
clock. It works as a tracking filter for all relevant
synthesized pixel clock frequencies.
7.12
Encoder
7.12.1
V
IDEO PATH
The encoder generates luminance and colour subcarrier
output signals from the Y, C
B
and C
R
baseband signals,
which are suitable for use as CVBS or separate Y and C
signals.
Input to the encoder, at 27 MHz clock (e.g. DVD), is either
originated from computer graphics at pixel clock, fed
through the FIFO and border generator, or a ITU-R BT.656
style signal.
Luminance is modified in gain and in offset (the offset is
programmable in a certain range to enable different black
level set-ups). A blanking level can be set after insertion of
a fixed synchronization pulse tip level, in accordance with
standard composite synchronization schemes. Other
manipulations used for the Macrovision anti-taping
process, such as additional insertion of AGC super-white
pulses (programmable in height), are supported by the
SAA7102 only.
To enable easy analog post filtering, luminance is
interpolated from a 13.5 MHz data rate to a 27 MHz data
rate, thereby providing luminance in a 10-bit resolution.
The transfer characteristics of the luminance interpolation
filter are illustrated in Figs 6 and 7. Appropriate transients
at start/end of active video and for synchronization pulses
are ensured.
Chrominance is modified in gain (programmable
separately for C
B
and C
R
), and a standard dependent
burst is inserted, before baseband colour signals are
interpolated from a 6.75 MHz data rate to a 27 MHz data
rate. One of the interpolation stages can be bypassed,
thus providing a higher colour bandwidth, which can be
used for the Y and C output. The transfer characteristics of
the chrominance interpolation filter are illustrated in
Figs 4 and 5.
The amplitude (beginning and ending) of the inserted
burst, is programmable in a certain range that is suitable
for standard signals and for special effects. After the
succeeding quadrature modulator, colour is provided on
the subcarrier in 10-bit resolution.
The numeric ratio between the Y and C outputs is in
accordance with the standards.
7.12.2
T
ELETEXT INSERTION AND ENCODING
(
NOT
SIMULTANEOUSLY WITH REAL
-
TIME CONTROL
)
Pin TTX_SRES receives a WST or NABTS teletext
bitstream sampled at the crystal clock. At each rising edge
of the output signal (TTXRQ) a single teletext bit has to be
provided after a programmable delay at input pin
TTX_SRES.
