
26
LC4.6E AA
7.
Circuit Diagrams and PWB Layouts
SSB: Audio Delay line (Lip sync)
EN
C1
1D
EN
C1
1D
2C1
14
13
11
10
9
8
7
6
5
4
3
2
1
0
2EN
32k-1
0
A
A,1D
12
A
G2
C2
G1
1+
CT=0
CTR8
(CT=255)Z4
2D 3
4
EN3
C2
G1
1+
CT=0
CTR8
(CT=255)Z4
2D 3
4
EN3
2V6
5V3
2V5
2V6
2V5
5V3
2V6
2V5
2V5
2V5
2V3
5V3
A
B
C
D
E
F
A
B
C
D
E
F
2580 B1
2581 D1
2582 B2
2583 B7
2584 B8
2585 F6
2586 F6
2587 D9
0V2
2V3
5V3
2V3
5V3
A2
2V6
2V6
A2
2V3
2V5
2V5
2V3
2V6
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
2V6
(1)
5V3
5V3
DFF
(1)
COUNTER
2V6
AUDIO DELAY LINE (Lip sync)
(1)
COUNTER
DFF
(1) NOT USED
2V6
2588 D9
3580 F5
3581 F6
4580 F2
4581 F2
4582 F2
4583 F2
4584 F2
4585 F2
4586 C9
4587 C9
4588 C9
4589 C9
4590 C9
4591 C9
4592 C9
4593 D9
5580 A1
2V6
2V6
A2
2V5
7580 B1
7581 F1
7582 B2
7583 C6
7584 C8
7585 F6
F580 A1
F584 F9
F585 F5
F586 F6
F587 D9
F588 D9
F590 B2
(1)
(1)
(1)
(1)
2V6
(1)
(1)
(1) NOT USED
2V3
2V6
2V6
2V6
2V3
5V3
2V6
(1)
RAM
32kx8
F584
4583
4585
F585
F586
F587
F588
4593
4592
4591
2585
4590
82p
+5VD
100n
2584
+5VD
+5VD
100n
2583
100n
2582
+5VD
28
27
F590
11
12
13
15
16
17
18
19
14
22
10
24
25
26
1
2
3
4
5
20
7582
CY62256LL-70ZC
21
23
6
7
8
9
2586
82p
2588
470p
2587
330p
18
17
16
15
14
13
12
20
5
6
7
8
9
10
11
1
19
7583
74HC573PW
2
3
4
19
18
17
16
15
14
13
12
20
3
4
5
6
7
8
9
10
11
1
7584
74HC573PW
2
+5VD
+5VD
100n
2581
100n
+5VD
2580
F580
1u0
5580
+5VD
13
9
16
VCC
+5VSW
15
1
2
3
4
5
6
7
M74HC590T
7581
11
12
10
8
GND
14
7
13
9
16
VCC
15
1
2
3
4
5
6
7580
11
12
10
8
GND
14
M74HC590T
4588
4589
4587
+5VD
4586
4584
4580
4581
4582
7585
BC847BW
47K
3581
470R
3580
I2SCLK
I2SDI1
I2SDO1
E_14710_018.eps
210105
3139 123 5837.1