Philips AZT9500, Service Manual

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SM5907AF – COMPRESSION-TYPE ANTI-SHOCK MEMORY CONTROLLER NPC
Pin Name Direction Description
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
1 VDD2 +2.6V supply voltage
2 UC1 NPC
↔
µP interface extension I/O line 1
3 UC2 NPC
↔
µP interface extension I/O line 2
4 UC3 NPC
↔
µP interface extension I/O line 3
5 UC4 NPC
↔
µP interface extension I/O line 4
6 UC5 NPC
↔
µP interface extension I/O line 5
7 NACS3 NPC
→
DRAM DRAM2 CAS control
8 TEST2 +2.6V test pin
9 CLK CD10
→
NPC 16.9344MHz clock input
10 VSS GND ground
11 YSRDATA CD10
→
NPC audio serial data input
12 YLRCK CD10
→
NPC audio serial L/R clock input
13 YSCK CD10
→
NPC audio serial bit clock input
14 ZSCK NPC
→
CD10 audio serial bit clock output
15 ZLRCK NPC
→
CD10 audio serial L/R clock output
16 ZSRDATA NPC
→
CD10 audio serial data output
17 YFLAG CD10
→
NPC signal processor IC RAM overflow flag
18 YFCLK GND crystal-controlled frame clock input
19 YBLKCK CD10
→
NPC subcode block clock signal output
20 RESET µP
→
NPC system reset input (active low)
21 ZSENSE NPC
→
µP interface status output
22 VDD1 +2.6V supply voltage
23 YDMUTE
→
NPC forced mute input
24 YMLD µP
→
NPC µP interface latch clock input
25 YMDATA µP
→
NPC µP interface serial data input
26 YMCLK µP
→
NPC µP interface shift clock input
27 A10/NCAS2 NPC
→
DRAM DRAM OE control output (active low)
28 CAS NPC
→
DRAM DRAM CAS control output (active low)
29 D2 NPC
↔
DRAM DRAM data input/output 2
30 D3 NPC
↔
DRAM DRAM data input/output 3
31 D0 NPC
↔
DRAM DRAM data input/output 0
32 D1 NPC
↔
DRAM DRAM data input/output 1
33 WE NPC
→
DRAM DRAM WE control output (active low)
34 RAS NPC
→
DRAM DRAM RAS control output (active low)
35 A9 NPC
→
DRAM DRAM address output 9
36 A8 NPC
→
DRAM DRAM address output 8
37 A7 NPC
→
DRAM DRAM address output 7
38 A6 NPC
→
DRAM DRAM address output 6
39 A5 NPC
→
DRAM DRAM address output 5
40 A4 NPC
→
DRAM DRAM address output 4
41 A0 NPC
→
DRAM DRAM address output 0
42 A1 NPC
→
DRAM DRAM address output 1
43 A2 NPC
→
DRAM DRAM address output 2
44 A3 NPC
→
DRAM DRAM address output 3
TA2120FN – Stereo Headphone Amplifier
Pin Name Direction Description
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
1 DBB NF
→
headphone-amp NF of DBB amplifier
2 ADD OUT headphone-amp
→
output of ADD amplifier
3 RF IN
→
headphone-amp terminal for ripple filter circuit
4 PWC
→
headphone-amp center amplifier on/off switch (open = on)
5 VCC +HP (+A) positive supply voltage
6 B headphone-amp
→
HP-socket output of power amplifier
7 C headphone-amp
→
HP-socket output of center amplifier
8 A headphone-amp
→
HP-socket output of power amplifier
9 GND GND ground of power amplifier
10 MIX OUT headphone-amp
→
output of power amplifier (mixed)
11 ALC IN
→
headphone-amp input terminal for ALC detector circuit
12 ALC DET
→
headphone-amp smoothing for ALC detection (GND = ALC off, open = ALC ON)
13 ATT
→
headphone-amp power amplifier gain switch (open/VCC = ATT off, GND = ATT on)
14 IN A
→
headphone-amp input of power amplifier
15 IN B
→
headphone-amp input of power amplifier
16 GND GND ground of input stage in power amplifier
17 BEEP IN µP
→
headphone-amp input terminal for beep sound
18 MUTE TC
→
headphone-amp terminal for mute smoothing
19 MUTE SW µP
→
headphone-amp power mute switch (GND/open = mute off, VCC = mute on)
20 POWER
→
headphone-amp power switch (VCC = power on, GND/open = power off)
21 BIAS headphone-amp
→
BIAS voltage
22 BIAS IN
→
headphone-amp filter terminal for BIAS circuit
23 DBB SW µP
→
headphone-amp DBB on/off switch (open/VCC = DBB on, GND = DBB off)
24 DBB OUT headphone-amp
→
Output of DBB amplifier (terminal for filter)