Philips ACT200, Service Manual

Page: 18 / 34

3 - 5 3 - 5
I/O Control circuit
Status register
Address register
Command register
Column buffer
Column decoder
Data register
Sense amp
Memory cell array Control
HV generator
Ro
w addres
s dec
oder
Logic control
BY / RY
V
CC
I/O1
V
SS
I/O8
to
WP
CE
CLE
ALE
WE
RE
BY / RY
Ro
w addres
s b
uf
fer
decoder
PIN ASSIGNMENT
(TOP VIEW)
PIN NAMES
I/O1 to I/O8 I/O port
CE Chip enable
WE Write enable
RE Read enable
CLE Command latch enable
ALE Address latch enable
WP Write protect
BY / RY Ready/Busy
GND Ground input
V
CC
Power supply
V
SS
Ground
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
NC
NC
V
CC
V
SS
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
BY / RY
RE
CE
NC
NC
V
CC
V
SS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs
are configured as shown in Figure 1.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the
operation mode command into the internal command
register. The command is latched into the command
register from the I/O port on the rising edge of the WE
signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading of either
address information or input data into the internal
address/data register.
Address information is latched on the rising edge of
WE if ALE is High.
Input data is latched if ALE is Low.
Chip Enable:
The device goes into a low-power Standby mode when CE goes High during a Read operation. The CE
signal is ignored when device is in Busy state ( BY / RY = L), such as during a Program or Erase operation, and
will not enter Standby mode even if the CE input goes High. The CE signal must stay Low during the Read
mode Busy state to ensure that memory array data is correctly transferred to the data register.
Write Enable:
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable:
The RE signal controls serial data output. Data is available t
REA
after the falling edge of RE .
The internal column address counter is also incremented (Address = Address + l ) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the
device.
Write Protect:
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy:
The BY / RY output signal is used to indicate the operating condition of the device. The BY / RY signal is in
Busy state ( BY / RY = L) during the Program, Erase and Read operations and will return to Ready state
( BY / RY
=
H) after completion of the operation. The output buffer for this signal is an open drain.
NC
NC
NC
NC
NC
GND
BY / RY
RE
CE
NC
NC
V
CC
V
SS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
NC
NC
V
CC
V
SS
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
Figure 1. Pinout
CE
WE
RE
WP
BY / RY
BLOCK DIAGRAM OF INTEGRATED CIRCUIT
NAND E
2
PROM - TC58512FT
Abbreviations and Pin-description of NAND E
2
PROM
TC58512FT