Circuit Diagrams and PWB Layouts
49
7.
DFI Panel: FPGA: Power & Control
DATA
GND
ASDI
DCLK
CS_
VCC
NC
NC
DATA
GND
ASDI
DCLK
CS
VCC
IFA1 A1
IFA2 B9
IFA3 C9
IFA4 D9
IFA5 C1
IFA6 I10
IFA7 G8
IFA9 G7
IFB1 C9
IFB2 C9
IFB3 F4
IFB4 F4
7F31 C8
7F32 I11
7F34-1 G9
7F34-2 G7
FF3G A3
FF3H B3
FF3J B3
IFB5 F5
IFB6 E6
IFB7 E6
cF01 B5
FF3P G9
FF3Q G11
FF58 D3
FF59 G7
FF69 G11
RESERVED
FPGA: POWER + CONTROL
3F83 G7
3F84 G11
5F25 D2
5F26 D2
5F49 F12
5F50 F13
5F51 A2
DEBUG
FOR
5F52 B10
5F53 A2
5F54 B2
5F55 A2
5F57 B2
5F58 C2
6F30 I11
6F31 G4
6F32 G4
6F33 G5
6F34 G6
6F35 G6
7F30 B10
3F06 G5
3F08 G6
3F10 G6
3F11 F7
3F14 D13
3F72 H11
FF3K C3
FF3L G11
FF3M G11
FF3N G11
3F78 F10
3F79 F10
3F80 G11
3F81 G9
3F82 G11
2FJN G8
2FJP B3
2FLC D2
2FLD D2
2FLE D2
3F85 G11
3F86 G10
5F23 B2
5F24 C2
2FLK H12
2FLL H12
3F02 G4
3F04 G4
3F05 F10
RESERVED
2FHR C3
2FHS C3
2FHT B3
2FJ7 F13
2FJ8 C2
2FJ9 C2
2FJA C3
3F73 I10
3F74 I10
3F75 I11
3F76 F7
2FJF C4
2FJJ C8
2FJK C11
2FJL C11
2FJM F7
13
14
A
B
C
2FLF D3
2FLG H12
2FLH H12
2FLJ H12
H
I
A
B
C
2FHJ B5
2FHK B5
2FHL B2
2FHM B2
2FHN C2
2FHP C2
2FHQ C3
11
12
13
14
1
2
3
2FJB C3
2FJC C3
2FJD C3
2FJE C3
8
9
10
11
12
D
E
F
G
1
2
3
4
5
6
7
8
9
10
2FGG B5
2FGH B5
2FGJ B6
2FGM B6
2FGN B6
2FGP B6
2FH1 A2
4
5
6
7
2FH2 A3
2FH3 A3
2FH4 A3
2FH5 A4
2FHA A3
2FHB B3
2FHC B3
2FHD B4
2FHE B4
2FHF B4
2FHG B4
2FHH B4
ACTIVE SERIAL DEBUG-CONNECTOR
D
E
F
G
H
I
1F00 F13
1F05 C12
2FGF B5
100p
2FLG
IFA7
6
4
3
7
8
FF59
EPCS4SI8
7F31
SCD
Φ
5
1
2
RES
RES
30R
5F26
RES
5F23
30R
5F53
30R
2FJP
4u7
10n
2FHS
FF3L
3F76
10K
30R
5F57
2FJ
A
10n
100p
2FLL
2FLK
10n
100p
2FLJ
2FLH
100p
2FHF
10n
2FHE
10n
IFB2
5F58
30R
3F86
RES
1K0
IFB1
SML-310
6F33
3F82
100R
10n
IFA6
2FJL
3F14
10K
FF3K
2FH4
10n
BC847BS
7F34-2
5
3
4
2FJF
10n
RES
RES
30R
5F51
3F05
1K0
2FJ7
10n
RES
30R
5F50
5F49
30R
10n
2FHH
10n
2FJC
IFA9
IFA1
IFA5
6F32
SML-310
4
5
6
7
8
9
5-147279-2
1F05
1
10
2
3
FF3N
12
13
14
1
2
9
8
16
10
3
4
5
6
11
EPCS16SI16N
7F30
SCD
Φ
15
7
5F54
30R
2FH5
10n
3F79
1K0
10n
2FJK
2FLC
4u7
3F06
470R
3F72
3K3
2FJJ
2FH1
1u0
RES 10n
FF3Q
4u7
2FHA
10n
2FHR
7
8
9
IFB4
1
10
2
3
4
5
6
5-147279-2
1F00
10n
2FHD
FF3M
6F31
SML-310
2FH3
10n
10n
2FHJ
BC847BW
7F32
10n
2FH2
2FJ8
4u7
2FJB
10n
FF58
2
6
1
BC847BS
7F34-1
2FJN
1u0
2FHM
47u
SML-310
6F30
10n
2FHQ
3F74
100K
2FHK
10n
3F83
33K
2FHG
10n
30R
5F55
5F25
30R
30R
5F52
3F02
470R
2FLE
10n
3F78
1K0
FF3G
IFB7
30R
5F24
IFA3
FF3P
2FHN
1u0
IFA4
2FHL
100u
4
V
100R
3F80
10K
3F81
10n
2FJD
2FHP
10n
cF01
10n
2FLF
3F85
100R
470R
3F04
SML-310
6F35
3F10
470R
470R
3F08
2FLD
10n
IFB3
6F34
SML-310
10n
2FHC
IFB6
IFA2
FF69
2FHB
1u0
2FHT
330u
6.3V
FF3J
3F75
100K
2FGM
10n
10n
2FGP
2FGN
10n
2FGJ
10n
10n
2FGH
10n
2FGG
2FGF
10n
3F11
100K
10K
FF3H
3F73
3F84
10n
100R
2FJE
IFB5
2FJ9
10n
2FJM
+1V2
+2V5
+2V5
+2V5
+2V5
TDO
+2V5
1u0
DCLK
CONF-DONE
nCONFIG
nCE
DATA0
nCSO
ASDO
+2V5
+1V2-FPGA
+2V5-STAB
+2V5
+2V5in-FPGA
TCK
+3V3
+3V3
+3V3
+1V2-PLL
+Vin-FPGA
+2V5out-FPGA
+2V5-STAB
+3V3
+2V5
+2V5
MP-LED1
MP-LED2
MP-LED3
MP-LED4
MP-LED5
CONF-DONE
SENSE+1V2-FPGA
ASDO
nCSO
DATA0
DCLK
+3V3
+3V3
+1V2
ASDO
nCONFIG
nCSO
DATA0
DCLK
TDI
TMS
AB05
AB05
H_16800_014.eps
180407
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