Circuit Diagrams and PWB Layouts
47
7.
DFI Panel: Clock
D
ATA
GND
ASDI
DCLK
CS_
VCC
GND
VDD
EOH
OUT
IFC6 C7
IFC7 G3
IFC8 G3
9F09 G3
IF13 F3
IFD8 D4
IF14 F2
IF29 B3
IFC0 C4
IFC1 C4
IFC2 C4
IFC3 B6
IFC5 C7
5F20 B6
5F21 E3
IFC9 F3
IFD1 G6
5F22 F6
5F80 B3
7F50 G3
7F51 G6
7F85 C3
7F86 C6
9F08 G3
H
A
RESERVED
2FD3 F3
2FD4 G5
3F26 C4
3FA9 D4
3FH0 C4
3FH1 C4
3FHV C7
3FHY C7
3FJA F2
3FJB G3
3FJC F6
8
9
10
11
12
A
B
C
D
E
F
G
12
1
2
3
4
5
6
7
2FD1 C3
2FD2 C6
1
2
3
4
5
6
7
8
9
10
11
Video-clock RESERVED
CLOCK
B
C
D
E
F
G
H
30R
+3V3
5F22
100R
3FHV
RES
1F43
1F33
1F42
IFC9
1F31
+3V3
9F09
IFC3
1F41
IFC7
1F48
2
1
4
3
DSO751SV
27M0
7F85
2FD2
100n
30R
5F21
1F32
1F47
IFC0
100n
2FD3
RES
9F08
3FJA
1K0
3FJC
33R
100R
3FA9
2FD4
100n
1F35
1F44
5F20
6
4
3
7
8
30R
Φ
SCD
7F50
EPCS4SI8
5
1
2
3FH1
100R
IF29
+3V3
IFD1
1F30
100n
2FD1
IFC1
IF13
+3V3
1
4
3
IF14
7F86
27M0
DSO751SV
2
1F34
IFC8
1F46
IFC2
1F45
RES
100R
3F26
33R
3FJB
1
2
3
4
7F51
50M
1F40
IFD8
1F49
30R
IFC6
5F80
3FHY
100R
RES
100R
3FH0
CLK-OSC1A
SS-OFF
IFC5
CLK-OSC1D
CLK-OSC2C
CLK-OSC1C
CLK-VIDEO
CLK-VIDEO-SS
CLK-SYSTEM-SS
SS-OFF
CLK-OSC1B
CLK-OSC1C
CLK-OSC2B
AB03
AB03
H_16800_012.eps
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