Philips 47PFL5403, Service Manual

Page: 100 / 115

Circuit Descriptions, Abbreviation List, and IC Data Sheets EN 100 LC8.2A LA 9.
9.5.2 Video Application
Figure 9-7 Block diagram video processing
“Block diagram video processing” shows the input and output
signals to and from the Trident Video Processor.
During analogue reception, a CVBS signal coming from the
analogue front-end is fed to the video processor via pin
CVBS1.
The video processor also interfaces the (side-) AV inputs, VGA,
CVI (HD) and HDMI input. Through the CVBS OUT connector,
a monitor output is foreseen.
9.5.3 Dynamic Frame Insertion (DFI)
In order to obtain 1080p @ 100 Hz, the same DFI panel is used
as in Q528.1A LA Service Manual.
Refer to figure “DFI implementation” for the LC08-specific
implementation of the DFI panel.
Figure 9-8 DFI implementation
Please not that in due time the DFI panel will be replaced by an
on-board Mediatek solution.
9.6 Audio Processing
Refer to the LC7.1A LA Service Manual.
For additional (future) China DTV implementation, refer to
figure “Block diagram audio processing”.
Figure 9-9 Block diagram audio processing
9.7 HDMI
9.7.1 Introduction
Refer to the LC7.1A LA Service Manual.
9.7.2 Implementation
The main HDMI receiver which is used is the Sil 9125 (Silicon
Image) third generation HDMI receiver (item 7N01 on the
SSB). In addition, the Sil 9185 HDMI switch (item 7M07) is
used for switching between the 3 HDMI inputs. Refer to figure
“HDMI implementation” for details.
Figure 9-10 HDMI implementation
When the HDMI receiver Sil9125 receives either RGB or
YCbCr 4:2:2 input signals, it will convert these signals to 24-36-
bit YCbCr 4:4:4 output signals. When it receives an YCbCr
4:4:4 input signal, it will just bypass this signal to the Trident
WX69 video processor.
CVB S 1
An a log
Front End
CVB S _RF
S C2_Y_CVB S _IN
VGA_R_IN
VGA_G_IN
VGA_B_IN
HDMI S IDE
HDMI B
HDMI C
HDMI A/DTV
HD_Y_IN
HD_PB_IN
HD_PR_IN
S VH S _Y_CVB S _IN
S VH S _C_IN
PR R 3
PC R
PC G
PC B
C
Y G 3
Y G1
PB B1
PR R1
DPA
HDMI YC b Cr R0X
R1X
HDMI
MAIN
R0X
R1X
R2X
TX
HDMI
AV IN
VGA
S IDE AV
CVI 1
CVB S OUT1 S C1 RF OUT CVB S
S WITCH
MONITOR OUT
TRIDENT
WX69
I_17760_054.ep s
040 3 0 8
Primary DLVDS
(51
pins)
12V
Secondary
DLVDS (41 pins)
Power Supply
100Hz
41 pin DLVDS
(with IIC)
LC08 SSB
AmbiLight FPGA
AmbiLight IIC out
DFI FPGA
bolt-on
HD/FHD 100/120 Hz
Panels
HD – Primary DLVDS only
FHD – Both primary and
Secondary DLVDS
Cascade IIC Left
AL
Box
Right
AL
Box
12V
I_17760_055.ep s
040 3 0 8
I_17760_056.ep s
040 3 0 8
I_17760_057.ep s
040 3 0 8