Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.
9.5.2
Multistandard TV Audio Processor, STV82x6 (U200)
Figure 9-3 Internal block diagram and pin configuration of the audio processor
Block Dia
g
ram
Pin Confi
g
uration
G_16510_064.ep
s
221106
Audio
AGC
Audio
A/D
A/D
SDA
SC
L
SI F
AI1L
AI1R
LS L
LSR
SW
Matrix
AI 2L
AI2R
AI3L
AI3R
Input
Stereo
MONOIN
Multi-Standard
Demodulator
Digital
Au dio
Matrix
Analog
S
o
ur
ce P
re
p
ro
c
e
ssing
F M, AM, A2
and NICAM
Loudspeaker Audio Processing
Smart Volume Control, ST WideSurround,
5-band Equalizer and Loudness,
Headphone Audio Processing
Sm art Volume Control,
B eeper and Subwoofer Output
Bass/Treble and Beeper
I2S Interface
Audio
S tereo
D/A
Audio
Stereo
D/A
Audio
S tereo
D/A
Vo l./
Low Noise
Audio Mute
1V
rms
HPL
HP R
Low Noise
Audio Mute
1V
rms
SC
K
SD
O
WS
I2C Interface
Gain
Audio
Matrix
Output
Analog
Low Noise
Audio Mute
Low Noise
Audio Mute
2V
rms
2V
rms
AO1L
AO1R
AO2L
AO2R
IRQ
ST
BU
S
0
BUS
1
HPD
0.5V
rms
2V
rms
2V
rms
2V
rms
Single Crystal
Clock Generation
Au dio Matrixing
A udio Processing
Demodulation
XT
I
XT
O
Po wer Supply Management
DC Regulators, Standby mode
I2C Bus Expander
In
p
u
t
SCART
s
So und IF
Ou
tp
u
tS
ca
r
ts
Headphone
Subwoofer
Lo udspeaker
Headphone
De tection
Mono In
S
tereo
Inte
rrup
t
S TV82x6
Digital Stereo
Re
qu
e
s
t
Fl
a
g
St
e
re
o
Fl
a
g
Bal.
Vol./
Ba l.
NC
NC
STV82x6D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SIF
VTOP
VREFIF
VDDIF
GNDIF
MONOIN
AO1L
AO1R
VDCC
GNDC
AI1L
AI1R
VMC1
VMC2
AI2L
AI2R
VDDA
GNDAH
AO2L
AO2R
VDDH
VREFA
AI3L
AI3R
BGAP
LSL
LSR
SW
IRQ
BUS0
BUS1
SCK
WS
ST
SDO
CKTST
VDD2
GND2
GNDP
VDDP
XTO
XTI
GNDSP
GND1
VDD1
MCK
SYSCK
RESET
REG
SDA
SCL
ADR
HPD
GNDSA
HPR
HPL
