10.
Circuit Diagrams and PWB Layouts
SSB: FPGA 1080p: Interface
C
5
4
3
12
11
10
9
8
1
3
12
11
10
9
8
7
6
G
H
E
C
A
i
s
prohi
b
ited witho
u
t the written con
s
ent of the copyright
owner.
A
B
C
D
E
F
G
H
I
10
All right
s
re
s
erved. Reprod
u
ction in whole or in p
a
rt
s
12
1
3
I
H
G
F
E
D
C
B
A
J
J
3
1
5
77
3
1
2
1
1
1
0
1
9
8
6
8
6
5
4
3
2
1
H
I
J
2
1
3
4
3
2
1
J
I
FPGA 10
8
0p : INTERFACE
G
FPGA -d
ua
l even LVD
S
-o
u
tp
u
t
D
9
B
3
F57 C5
F
3
F59 C5
3
F60 C5
3
F61 C5
3
F62 D5
3
F6
3
D5
3
F64 D5
3
F65 D5
3
F66 D5
3
F67 D5
3
F6
8
E5
3
F69 E5
3
F70 E5
9F
3
5 B9
9F
3
6 B9
9F
3
7 B9
9F
38
C9
9F
3
9 C9
9F40 C9
9F41 C9
9F42 C9
9F4
3
C9
9F44 D9
9F45 D9
9F46 D9
3
F46 D2
2
3
F4
8
D2
4
3
F50 D2
6
3
F52 E2
1
3
F54 B5
3
F55 B5
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
A
B
5
FPGA -
b
yp
ass
FPGA -
s
ingle/d
ua
l odd LVD
S
-o
u
tp
u
t
11
7
3
F56 C5
C
3
F5
8
C5
D
E
A
B
C
D
E
3
F
3
5 B2
3
F
3
6 B2
3
F
3
7 B2
3
F
38
B2
3
F
3
9 C2
3
F40 C2
3
F41 C2
3
F42 C2
3
F4
3
C2
3
F44 C2
3
F45 D2
3
F47 D2
3
F49 D2
3
F51 E2
3
F5
3
B5
3
F4
8
120R
1
8
0R
3
F47
3
F59
1
8
0R
3
F46
1
8
0R
3
F62
1
8
0R
1
8
0R
3
F56
3
F70
1
8
0R
3
F61
1
8
0R
9F45
1
8
0R
3
F6
3
120R
3
F64
3
F52
1
8
0R
1
8
0R
3
F6
8
1
8
0R
3
F44
3
F4
3
1
8
0R
1
8
0R
3
F41
3
F
3
6
120R
3
F50
1
8
0R
1
8
0R
3
F55
120R
3
F57
3
F
3
7
1
8
0R
1
8
0R
3
F
3
5
1
8
0R
3
F65
9F40
3
F51
120R
9F46
3
F69
120R
9F44
9F4
3
9F
3
7
9F
38
3
F
3
9
120R
3
F
38
1
8
0R
3
F40
1
8
0R
9F
3
9
120R
3
F54
3
F5
3
1
8
0R
DATE
NAME
1
S
UPER
S
.
CLA
SS
_NO
2
2
5
B
P
E
M
A
N
T
E
S
N
H
C
4
3
3
PC
33
2
DC
3
07
3
67
YiPing G
u
o
200
8
-04-1
8
3
1
3
0
27
200
8
-02-2
8
ROYAL PHILIP
S
ELECTRONIC
S
N.V. 2007
200
8
-04-25
A
3
PB522
PCB
S
B PB522 He
a
lthc
a
re
3
1
3
9 2
83
3
00
3
CHECK
120R
3
F42
9F
3
6
9F42
9F
3
5
9F41
120R
3
F60
3
F49
1
8
0R
3
F45
120R
3
F66
120R
3
F67
3
F5
8
1
8
0R
RxP
3
oE-_G9
Tx
8
5
3
5oE+
RxP
3
oE+_G
8
1
8
0R
RxP
3
oA+_B
8
Tx
8
5
3
5oB-
RxP
3
oB-_B7
Tx
8
5
3
5oB+
RxP
3
oB+_B6
Tx
8
5
3
5oD-
RxP
3
oD-_B1
Tx
8
5
3
5oD+
RxP
3
oD+_B0
Tx
8
5
3
5oE-
Tx
8
5
3
5oC+
RxP
3
oC+_B4
Tx
8
5
3
5oCLK+
RxP
3
oCLK+_B
3
Tx
8
5
3
5oCLK-
RxP
3
oCLK-_B2
Tx
8
5
3
5oA-
RxP
3
oA-_B9
Tx
8
5
3
5oA+
RxP
3
eD+_R
8
RxP
3
eCLK+_G1
RxP
3
eCLK-_G0
RxP
3
eC-_G
3
RxP
3
eC+_G2
RxP
3
eA-_G7
RxP
3
eA+_G6
Tx
8
5
3
5oC-
RxP
3
oC-_B5
TxF
T
TxFPGAeC-
T
TxFPGAeA-
RxP
3
eB-_G5
RxP
3
eB+_G4
RxP
3
eE-_R7
RxP
3
eE+_R6
RxP
3
eD-_R9
TxFPGAoCLK-
TxFPGAoD-
T
TxFPGAoE-
T
T
TxFPGAeB-
T
TxFPGAeE-
T
TxFPGAeD-
TxFPGAeCLK-
RxP
3
oD-_B1
RxP
3
oE+_G
8
RxP
3
oE-_G9
TxFPGAoA-
T
TxFPGAoB-
T
TxFPGAoC-
T
TxF
RxP
3
oA+_B
8
RxP
3
oA-_B9
RxP
3
oB+_B6
RxP
3
oB-_B7
RxP
3
oC+_B4
RxP
3
oC-_B5
RxP
3
oCLK-_B2
RxP
3
oCLK+_B
3
RxP
3
oD+_B0
1
8
710_526_090
8
24.ep
s
090
8
24