Philips 32FD9944/01S Service Manual Download Page 107

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Circuit Descriptions and List of Abbreviations

9.5.5

Mute (Diagram A2 to A6)

A mute switch (item 7302) is provided at the PWM inputs (item
7315, LM311). This switch is controlled by the
AUDIO_ENABLE line, which checks the availability of the
+9V_STBY voltage.

9.5.6

Protections

Short-circuit Protection (Diagram A3)
A protection is made against a too high temperature of
transistor 7355 in case of a short-circuit of output FET 7365-1.
Transistor 7340 is sensing the current through transistor 7355
via R3355, and activates the DC-protection line (see below) in
case the current becomes too high. This is the same for all four
amplifier parts.

DC-protection (Diagram A7)

Figure 9-20 DC Protection

Because of the symmetrical supply, a DC-blocking capacitor,
between the amplifier and the speaker, is not necessary.
However, it is still necessary to protect the speaker for DC
voltages.
The following protections are therefore implemented:
•

Via R3765 and R3775, each stabilised supply voltage line
(via items 7735 and 7745) is checked on deviations.

•

Via R3770/3771/3780/3781, each amplifier output is
checked for DC-voltage.

Via R3765/3775, a virtual earth is imposed on point A. When
one of the supply voltages deviates, a DC voltage will occur on
this point. If point A is positive, T7751 will conduct. If it is
negative, T7761 will conduct.
Both cases will make T7735 conduct, so that the DC-PROT
signal will be made high. This ensures that the power supply is
rapidly trimmed back.
Capacitor C2760 will ensure that only DC-signals at point A will
activate the protection.

9.6

LED/Switch Panel (Diagram LD)

This panel contains:
•

The red and green status LEDs,

•

The RC input receiver,

•

The light sensor, and

•

The 'on/off' switch.

All signals on this panel come directly from the SCAVIO panel:
•

The LED and sensor signals (RED_LED, GREEN_LED
and LIGHT_SEN_IN) are routed to the OTC. When a
F21RE Receiver box is connected, the sensor signal is
routed to the OTC of this box (via UART), where it will
control the HOP via I

•

The RC signal (RC_IN) is routed to the OTC, the VGA1
connector, and the RC-out cinch connector.

•

The signals to (+9V_STBY) and from (+9V_STBY_SW) the
'on'/'off' switch are routed to the PSU board.

9.7

Plasma Display Panel (PDP)

9.7.1

General

The PDP, which is used in the FM24, is a product of Fujitsu
Hitachi Plasma Display Ltd (FHP). When defect, a new panel
must be ordered, and after receipt, the defective panel must be
send for repair in the packing (flight case) of the new ordered
panel.

9.7.2

Operation

Principle
Plasma displays work by applying a voltage between two
transparent display electrodes on the front glass plate of the
display. The electrodes are separated by an MgO dielectric
layer and surrounded by a mixture of neon and xenon gases.
When the voltage reaches the 'firing level', a plasma discharge
occurs on the surface of the dielectric, resulting in the emission
of ultra violet light.
This UV light then excites the phosphor material at the back of
the cell and emits visible light. Each cell or sub-pixel has red,
blue or green phosphor material and three sub-pixels combine
to make up a pixel. The intensity of each colour is controlled by
varying the number and width of voltage pulses applied to the
sub-pixel during a picture frame. This is implemented by
dividing each picture frame into sub-frames. During a sub-
frame, all cells are first addressed - those to be lit are pre-
charged to a specific address voltage - then during the display
time the display voltage is applied to the entire screen lighting
those that were addressed.
Each sub-frame has a weighting ranging from 1 time unit to 128
time units for a typical eight sub-frame arrangement (Time Unit
depends on size and number of pixels on the screen). This is a
purely digital PWM control mechanism, which is a key
advantage as it eliminates any unnecessary digital to analogue
conversions, making the PDP technology ideal for the all-digital
age.

Achieving High Resolution
While conventional technology, as found in standard VGA
resolution screens, uses 2 display electrodes for each
horizontal line, applying the same method to achieve higher
resolution (>1000 horizontal lines) brings inherent problems.
Firstly, the number of electrodes would need to be doubled
which would require very high precision production processes.
Secondly, the cell aperture ratio would reduce resulting in lower
brightness. In addition, either the driving scheme would have to
operate with double the speed, again introducing significantly
higher cost, or a dual-scan technique would have to be
introduced. With dual-scan, twice as many driving ICs would be
required. In summary, implementing high resolution with
conventional technology would result in lower brightness and
increased costs.

ALiS Technology
To achieve high brightness as well as cost-effectiveness, FHP
developed ALiS (Alternate Lighting of Surfaces) Technology.
ALiS is based on 3 principles:
•

Odd and Even lines are displayed separately

•

The non-lighting area between the cells is utilised

•

The number of electrodes = the number of horizontal
display lines + 1

Despite the smaller cell size, the aperture ratio can be
increased from 40% to 65% meaning that the screen is
inherently brighter. Another spin-off benefit is that the lighting
duty is reduced to 50% (odd fields and even fields lit for half of
each frame) meaning that a significantly improved phosphor
lifetime can be expected.

For more information, see http://www.fme.fujitsu.com/
products/plasma/01.html

OUT_LH

OUT_RH

3770

3780

OUT_LL

OUT_RL

3771

3781

VCC_10_POS

+9V_STBY

VCC_10_NEG

3775