VMP2
Introduction
ID 24855, Rev. 02
Page 1 - 5
© 2002 PEP Modular Computers GmbH
1.2 Board Overview
The VMP2 is a 3U VME CPU board featuring a powerful CPU (number cruncher). The
design is based on the new highly integrated Motorola PowerPC processor MPC8245,
which integrates a PCI interface and several peripherals inside one Chip.
Four standard memory configurations (32 MB, 64 MB, 128 MB and 256 MB SDRAM)
are available. Flash memory for integrating the initial bootloader and ROMable operat-
ing systems are provided . Additionally, NV SRAM or a Disk-On-Chip (by M-Systems)
can be placed on a DIL socket for special purposes.
The board controls the VMEbus through the Tundra UNIVERSE II PCI-VME bridge
which is an industrial standard for connecting the PCI bus to the VME. Improved VME-
bus master and VMEbus slave performance with an increase of FIFO depth and opti-
mized DMA transfer are some of the outstanding features of this device.
The VMP2 is also able to communicate with the environment through a Fast Ethernet
interface and two serial interfaces at the front side of the board. One of the serial inter-
faces is a RS232 full modem interface while the other is a software-configurable
RS232/RS485 port. These UARTS support baud rates up to 1.5 Mbps and are software
compatible with the 16550 UART from National Semiconductor. They contain 128 Byte
Transmit FIFO and 128 Byte Receive FIFO for reducing the bandwidth requirement of
the CPU.
The Ethernet is realized with the Intel 82559 with full duplex support at both 10/100
Mbps possible. This Fast Ethernet controller with an integrated 10/100 Mbps physical
layer device is the foremost solution for PCI board LAN designs. It combines low power
consumption with a small package design which is ideal for power and space con-
strained environments.
Anticipating the VMP2's use in data critical applications, the memory data path contains
a selectable in-line ECC controller which can provide SDRAM single-bit error correct or
double-bit error detect.
For mass data transmission a dual channel DMA controller is provided. It can be
programmed directly or through the use of descriptor chains located in memory. Data
can thus be moved from PCI to memory or vice versa, memory to memory, or PCI to
PCI.
The MPC8245 supports processor control and visibility through the JTAG/COP
(common on-chip processor) interface that is available on the VMP2. Utilizing third party
tools, the developer can access and control the processor. It also has standard IEEE
1149.1a-1993 compliant boundary scan capability. The ECC data path has a mecha-
nism to manually inject errors into memory for use with maintenance and diagnostic
utilities. Furthermore a watch point and capture register on the internal bus and a set of
address attributes on the external memory and PCI buses facilitate debugging analysis.
VME interface
In addition to the standard functionality required by a VME CPU, the VMEbus interface
(Tundra Universe 2) provides:
•
automatic First-Slot detection
•
integral FIFO buffers for multiple transactions in both directions
•
programmable DMA controller with linked list support.
•
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