Hardware Setup
13
Cache Configuration
The mainboard has a write-back caching scheme. You can order 256KB
or 512KB Level 2 Pipelined Burst cache onboard to improve the system
performance.
Cache Size and RAM Locations
Cache Size
Cache RAM
TAG RAM
Cacheable
Range
256KB
32K x32, 2 pcs
on U12, U15
16K x 8
on U18
64 MB
512KB
64K x 32, 2pcs
on U12, U15
16K x 8
on U18
128 MB
Multi I/O Port Addresses
Default settings for multi-I/O port addresses are shown in the table
below.
Port
I/O Address
IRQ
Status
LPT1*
378H
7
ECP + EPP
COM1
3F8H
4
COM2
2F8H
3
* If default I/O port addresses conflict with other I/O cards (e.g. sound
cards or I/O cards), you must adjust one of the I/O addresses to avoid
address conflict. (You can adjust these I/O addresses from the BIOS.
Note:
Some sound cards have a default IRQ setting for IRQ7, which
may conflict with printing functions. If this occurs do not use
sound card functions at the same time you print.
