Panasonic TY-FB11DHD, Service Manual

Page: 13 / 26

13
6 Block Diagram
6.1. HSC-Board Block Diagram
F
TCK
TMS TCK
TDI
TDI
H
TDO
V
CS
F
TDO
V H
CS
F
TDO
TDI
V
H
TCK
+1.8V
+3.3V_B
+3.3V_A
+1.5V
+3.3V_A
+3.3V_A
+3.3V
TP3401
+3.3V_A
D3304
D3303
+3.3V_A
+3.3V_A
TP3402
+3.3V_A
D3704
+3.3V_A
+3.3V_B
+3.3V_A
+3.3V_A
+3.3V_A
D3701
TP3501
+3.3V_A
TP3701
+1.8V
TP3801
TP3802
+3.3V_A
C
7 2
A
8 1
E
6 9 4 3
F
5
B
D
+9V
FOR
FACTORY
USE
12
VCC
11
OUT
IC3306
SDI
AVR+1.2V
3
+1.2V
AUDIO DAC
IC3305
3
IC3410
IC3504
AMP
5
IC3411
IC3412
Q3605
SDI OUTPUT
CLOCK
GEN
Q3601
6
STBY+5V
Q3603
JK3302
SDO_P
3
MUTE
SDO_N
2
TXOB+
LINKA[0-9]
10bit data bus
IIC DAT
AUDIO
SERIAL OUT
5
6
LEVEL SHIFT
VDD
3
DESERIALIZER(S->P)
TD2+
IC3408
5
SDOUT_TDO
TCLK1+
SDA
TCLK1-
TXOC+
PLL LOCK
CE VOUT
3
MASTER/SLAVE_L
S2P[0-19]
PCLK
ERR_A
BUFFER
BUFFER
2
SMPTE
2 PLL
DVB_ASI
P_CLK
RESET
A14
LINKA_CLK
5
39
2
38
5
SCLK_TCK
F
6
IC3405
LINKA_LOCK
V
CS_L_TMS
SDIN_TDI
DDI-1-N
VCC
VD
WP
LVDS_TX
4
SDI_P
HD
A15
SCL
HD
TE2+
H1
TE2-
SDA
1
VCC
5
8
7
PARALLEL TO SERIAL
HD
SLOT15V
VD
TC2+
RESET
TD2-
FPGA
+3.3V_A
5
8
SDI INPUT
+2.5V
6
JK3301
5
PLL_
VCC VCC
A13
A9
EQUALIZER
3
5
47
4
DATA ERROR
46
AVR+1.8V
SERIAL
DATA[2]
4
AVR+1.5V
EEPROM
TXCLK0
A10
A7
1
IC3304
VIN
1
IC3403
SLOT15V
H2
IC3404
IC3302
TXOD-
VCONT
TXOD+
A22
B37
VOUT
TXCLK1
B24
+1.8V
B25
Y[0-9]
B38
X3301
3
SDO_P
VCO
Pb[0-9]
6
TDI
TMS
+3.3V
F
IC3406
Pr[0-9]
H
H
IIC SCL
BUFFER
TXOA-
TXOB-
TCK
6
BUFFER
TDO
B11
IC3407
7
TDI
51
63
TB2+
A28
2
50
B12
TC2-
A8
A26
TXOE-
62
IC3501
TXOE+
R
A4
A12
IC3502
LVDS_
VCC
L
3
53
4
41
Q3602
PROM(FPGA)
40
52
LOCK
B23
Q3604
A5
SRQ
7
SERIAL IN
SCL
2
VCO_P
1
H0
3.3V
1
TXOA+
PLUG_DET
7
13
TCK
5
BUFFER
IC3310
1
TXOC-
TMS
8
AIN+
RESET
12
FOR
FACTORY
USE
TDO
+9V
TO
SLOT1,
SLOT2
BIN+
B28
7
SERIAL
DATA[2]
AOUT
B21
IC3303
TA2+
BOUT
A21
TA2-
IC3402
L
V
+9V
TB2-
1
R
DDI-1-P
EQUALIZER
SDO_N
DATA ERROR
LINEB[1N0-IN9]
10bit data bus
2
DVB_ASI
P_CLK
JK3702
SDO_P
SDOUT_TDO
X3701
DDI-1-P
SDI OUTPUT
SERIAL IN
SDI INPUT
2
VCO_P
CS_L_TMS
1
SDIN_TDI
DDI-1-N
IC3706
13
D_ERR
3
DESERIALIZER(S->P)
LOCK
5
3
SERIAL
DATA[2]
7
SDO_P
4
SERIAL
DATA[2]
VCO
IC3704
IC3702
IC3703
F
6
BUFFER
V
MASTER/SLAVE_L
PLL LOCK
LINEB[1N0-IN9]
PCLK
SMPTE
BUFFER
IC3705
2
SCLK_TCK
5 3
JK3701
6
VCC
6
BUFFER
5
SDI_P
SERIAL OUT
8
H
RESET
12
TXEA-
69
TB1+
68
65
TXEB+
B3
TC1-
B6
TXEE-
TXEA+
59
58
70
TD1+
TA1+
TA1-
64
TB1-
A3
TXED-
TE1+
TXED+
TXEC+
TXEB-
TD1-
57
TE1-
56
A2
B2
B14
B9
B5
71
PARALLEL TO SERIAL
B15
TC1+
B8 TXEC-
5 4
AVR+1.8V
VIN
VCONT 1
IC3505
VOUT
+1.8V
2 3
AVR+3.3V
VIN
IC3801
VOUT
TXEE+
LINKB[0-9]
LINKB[0-9]
10bit data bus
LINKA[0-9]
Pb[0-9]
Y[0-9]
Pr[0-9]
DATA FORMATTER
Y[0-9]
Pb[0-9]
Pr[0-9]
Y[0-9]
Pb[0-9]
Pr[0-9]
LVDS_CLK
4
IC3401
5
VCC
FPGA PROG
VOUT
PROG_B
PROG_B
ERR_B
LINKB_LOCK
LINKB_CLK
D_ERR
VD
HSC Dual Link HD-SDI
LINK B
LINK A
TY-FB11DHD
HSC-Board Block Diagram TY-FB11DHD
HSC-Board Block Diagram