Panasonic PV-DF2700-K, Service Manual, Page: 373 / 398

NOTE:
FOR SCHEMATIC DIAGRAM AND CIRCUIT BOARD LAYOUT NOTES,
REFER TO BEGINNING OF SCHEMATIC SECTION.
COMPARISON CHART
OF MODELS & MARKS
A
B
Z
MODEL MARK
Not Used
PV-DF2700-K
Not Used
Pin No. I/O
I 1
Signal Name Description
VDD +3.6V
O 2 LA4 Memory address 4
Memory address 5
Memory address 6
Memory address 7
Memory address 8
Memory address 9
Memory address 10
Memory address 11
Memory address 12
Memory address 13
Memory address 14
Memory address 15
Memory address 16
Memory address 17
Memory address 18
Memory address 19
Memory address 20
Memory address 21
O 3 LA5
O 4 LA6
O 5 LA7
O 6 LA8
O 7 LA9
- 8 VSS Ground
Ground
Ground
Ground
I 9 VDD +3.6V
O 10 LA10
O 11 LA11
O 12 LA12
O 13 LA13
O 14 LA14
O 15 LA15
O 16 LA16
- 17 VSS
I 18 VDD +3.6V
O 19 LA17
O 20 LA18
O 21 LA19
O 22 LA20
O 23 LA21
I 24 /RESET Reset : low
- 25 TDMDX/RSEL (Not used)
(Not used)
(Not used)
(Not used)
(Not used)
(Not used)
(Not used)
(Not used)
(Not used)
(Not used)
(Not used)
(Not used)
(Not used)
(Not used)
- 26 VSS
I 27 VDD +3.6V
- 28 TDMDR
- 29 TDMCLK
- 30 TDMFS
/TDMTSC - 31
O 32 TWS Audio transmit frame sync
O 33 TSD0 Audio serial data
- 34 VSS
I 35 VDD +3.6V
- 36 TSD1
- 37 TSD2
- 38 TSD3
I/O 39 MCLK Audio master clock
Audio transmit bit clock I/O 40 TBCK
O 41 SPDIF IEC958 audio data
- 42 NC
- 43 VSS Ground
Ground
I 44 VDD +3.6V
- 45 RSD
- 46 RWS
- 47 RBCK
- 48 APLLCAP
I 49 XIN 27MHz clock
- 50 XOUT
I 51 VDD +3.6V
- 52 VSS
O 53 DMA0 SDRAM address 0
SDRAM address 1
SDRAM address 2
SDRAM address 3
SDRAM address 4
SDRAM address 5
O 54 DMA1
O 55 DMA2
O 56 DMA3
O 57 DMA4
O 58 DMA5
I 59 VDD +3.6V
Pin No. I/O
- 60
Signal Name Description
VSS Ground
Ground
O 61 DMA6 SDRAM address 6
SDRAM address 7
SDRAM address 8
SDRAM address 9
SDRAM address 10
SDRAM address 11
O 62 DMA7
O 63 DMA8
O 64 DMA9
O 65 DMA10
O 66 DMA11
- 67 VSS
I 68 VDD +3.6V
O 69 /DCAS Column address strobe : low
- 70 /DOE (Not used)
(Not used)
(Not used)
O 71 /DWE Write enable : low
O 72 /DRAS0 Row address strobe : low
- 73 /DRAS1
- 74 /DRAS2
I 75 VDD +3.6V
- 76 VSS Ground
I/O 77 DB0 SDRAM data 0
SDRAM data 1
SDRAM data 2
SDRAM data 3
SDRAM data 4
SDRAM data 5
I/O 78 DB1
I/O 79 DB2
I/O 80 DB3
I/O 81 DB4
I/O 82 DB5
I 83 VDD +3.6V
- 84 VSS Ground
Ground
Ground
I/O 85 DB6 SDRAM data 6
SDRAM data 7
SDRAM data 8
SDRAM data 9
SDRAM data 10
SDRAM data 11
SDRAM data 12
SDRAM data 13
SDRAM data 14
SDRAM data 15
SDRAM chip select : low
SDRAM chip select : low
I/O 86 DB7
I/O 87 DB8
I/O 88 DB9
I/O 89 DB10
I/O 90
VSS
DB11
VDD
- 91
I 92
DB12
+3.6V
I/O 93
DB13 I/O 94
DB14 I/O 95
DB15 I/O 96
O 97 /DCS1
- 98 VSS
I 99 VDD +3.6V
O 100 /DCS0
O 101 DQM Data input/output mask
O 102 DSCK SDRAM clock
- 103 VSS Ground
Ground
I 104 VDD +3.6V
I 105 DCLK 27MHz clock
O 106 YUV0 YUV data 0
YUV data 1
YUV data 2
YUV data 3
YUV data 4
YUV data 5
YUV data 6
YUV data 7
O 107 YUV1
O 108 YUV2
O 109 YUV3
O 110 YUV4
I 111 VDD +3.6V
- 112 VSS
I 113 YUV5
I 114 YUV6
I 115 YUV7
I 116 PCLK2XSCN 2X pixel clock
pixel clock I/O 117 PCLKQSCN
I/O 118 /VSYNCH V-sync signal
I/O CHART OF IC8000
Pin No. I/O
I/O 119
Signal Name Description
/HSYNCH V-sync signal
- 120 VSS Ground
Ground
Ground
I 121 VDD +3.6V
+3.6V
+3.6V
I/O 122 HD0 Host data 0
Host data 1
Host data 2
Host data 3
Host data 4
Host data 5
Host data 6
Host data 7
Host data 8
Host data 9
Host data 10
Host data 11
Host data 12
Host data 13
Host data 14
Host data 15
I/O 123 HD1
I/O 124 HD2
I/O 125 HD3
I/O 126 HD4
I/O 127 HD5
I/O 128 HD6
- 129 VSS
I 130 VDD
I/O 131 HD7
I/O 132 HD8
I/O 133 HD9
I/O 134 HD10
I/O 135 HD11
I/O 136 HD12
I/O 137 HD13
- 138 VSS
I 139 VDD
I/O 140 HD14
I/O 141 HD15
- 142 /HWRQ (Not used)
(Not used) - 143
I/O 144
/HRDQ
Host interrupt
I 145
HIRQ
/HRST Host reset : low
I 146 HIORDY Host I/O ready
- 147 VSS Ground
I 148 VDD +3.6V
O 149 /HWR
/HRD
Host write request : low
Host read request : low I 150
I 151 /HIOCS16 Device 16-bit data transfer
O 152 /HCS1FX Host select 1
Host select 3
Host address 0
Host address 1
O 153 /HCS3FX
I/O 154 HA0
I/O 155 HA1
- 156 VSS Ground
Ground
Ground
I 157 VDD +3.6V
I/O 158 HA2 Host address 2
I 159 VPP Peripheral protection voltage
I/O 160 AUX0 I2C serial data
I2C serial clock I 161 AUX1
O 162 AUX2 DVD ready (Busy : low)
- 163 VSS
I 164 VDD +3.6V
- 165 AUX3 (Not used)
(Not used)
(Not used)
I 166 AUX4 DVD chip select : low
O 167 AUX5 Serial data 1
Serial data 0
Serial clock
I 168 AUX6
I 169 AUX7
O 170 Output enable : low
- 171 VSS
/LOE
I 172 VDD +3.6V
- 173 /LCS0
- 174 /LCS1
O 175 /LCS2 Clock
O 176 /LCS3 Memory chip select : low
- 177 VSS Ground
Pin No. I/O
I/O 178
Signal Name Description
LD0 Memory data 0
Memory data 1
Memory data 2
Memory data 3
Memory data 4
Memory data 5
Memory data 6
Memory data 7
Memory data 8
Memory data 9
Memory data 10
Memory data 11
Memory data 12
Memory data 13
Memory data 14
Memory data 15
I/O 179 LD1
I/O 180 LD2
I/O 181 LD3
I/O 182 LD4
I 183 VDD +3.6V
- 184 VSS Ground
I/O 185 LD5
I/O 186 LD6
I/O 187 LD7
I/O 188 LD8
I/O 189 LD9
I/O 190 LD10
I/O 191 LD11
- 192 VSS Ground
I 193 VDD +3.6V
I/O 194 LD12
I/O 195 LD13
I/O 196 LD14
I/O 197 LD15
O 198 /LWRLL Write enable : low
- 199 /LWRHL (Not used)
(Not used)
(Not used)
- 200 VSS Ground
Ground
I 201 VDD +3.6V
- 202 NC
- 203 NC
O 204 LA0 Memory address 0
Memory address 1
Memory address 2
Memory address 3
O 205 LA1
O 206 LA2
O 207 LA3
- 208 VSS
IC8002 DETAIL BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
GND
D
Q
CP
F/F
Q
D
CP
F/F
D
Q
CP
F/F
Q
D
CP
F/F
D
Q
CP
F/F
Q
D
CP
F/F
D
Q
CP
F/F
Q
D
CP
F/F