Panasonic DMR-EH59GC, Service Manual

Page: 49 / 104

49
11.2. Analog Video Block Diagram
(SW17C)
a
b
(SW17V)
a
b
(SW17Y)
a
b
14
15
JK3001
REAR JACK
AV4
VIDEO
IN
4
3 1
2 4
3
S-VIDEO IN JK3001
S-VIDEO
AV4
Y
C
AV4 V
AV4 Y
AV4 C
35
39
43
AV4 V
AV4 Y
AV4 C
CLAMP
BIAS
CLAMP
AV4 V
AV4 Y
AV4 C
DMR-EH59GA/GC/GN
Analog Video Block Diagram
V/Y IN DM
CPN CIN DM
MAIN P.C.B.
1.0V
2.3V
5V
:PB SIGNAL :REC SIGNAL
CLAMP
V
TUNER
30
INTERLACE
PROGRESSIVE/
VIDEO OUT
COMPONENT
Y
PB
PR
1
4
JK3903
3
2
RED/C 15
VIDEO/Y 19
GREEN 11
(TV)
AV1
BLUE 7
21PIN JACK
JK3901
OUT
C
Y
S-VIDEO
JK3001
9
10
OUT
VIDEO OUT
JK3001
15
13
(DECODER/EXT)
AV2
VIDEO 19
21PIN JACK
JK3901
U/V TUNER
TU7802
17
OUT
VIDEO
DIGITAL P.C.B.
TO
P59001 P7402
71
75
P7402 P59001
P59001 P7402
84
LOGIC
IIC BUS
SDA
89
SCL
88
SECTION
TIMER
FROM/TO
IIC DATA
IC7501- 30
29 IC7501-
IIC CLK
(SW10)
CLAMP
CLAMP
CLAMP
CLAMP
BIAS
CLAMP
OUT
ADC
V/Y
83
OUT
C-ADC
81
TUNER V
AV2 V/Y
AV2 R/C
AV3 V
AV3 C
AV3 Y
AV1 V
CIRCUIT
SWITCH
SELECT
OUTPUT
ADC
OUT
V
AV2
28
SV2
e
d
c
b
a
OUT
V/Y/C
AV1
26
SV1
e
d
c
b
a
a
b
(SW9)
OUT
V
24
23
a
b
(SW8)
OUT
C
22
(SW7)
a
b
OUT
Y
20
19
OUT
G
AV1
17
6MHz
(SW5)
12MHz
a
b
c
15
OUT
Y
COMP
14
(SW6)
a
b
c
d
OUT
B
AV1
12
OUT
B-Y
COMP
11
6MHz
(SW4)
12MHz
a
b
c
d
OUT
R-C
AV1
9
(SW3)
a
b
c
(VIDEO PROCESSOR)
IC3001
OUT
R-Y
COMP
7
(SW2)
a
b
c
(SW1)
12MHz
6MHz
CLAMP
BIAS
CLAMP/
CLAMP
BIAS
CLAMP/
+
LPF
6MHz
CLAMP
BPF
6MHz
BIAS
a
b
CLAMP
BIAS
c
b
a
AV2 V/Y
AV2 B
AV2 G
AV2 R/C
AV3 V
AV3 C
AV3 Y
AV1 V
AV2 V/Y
< RGB CPSV >
AV2 B
AV2 G
AV2 R/C
AV3 V
AV3 C
AV3 Y
31
5
3
1
(DECODER/EXT)
AV2
VIDEO/Y
BLUE
GREEN
RED/C
20
7
11
15
21 PIN JACK
JK3901
VIDEO IN
37
S-VIDEO IN
45
AV3
JK3003
FRONT JACK
AV3
JK3002
FRONT JACK
41
2
1
4
3
2
1
4
3
33
99
97
95
93
91
AV1 VIDEO
(TV)
AV1
20
21 PIN JACK
JK3901
FROM
DIGITAL P.C.B.
BPBOUT DM
GPYOUT DM
RPROUT DM
Y OUT DM
C OUT DM
P59001
67
P7402
P7402 P59001
63
59
P59001 P7402
51
P59001 P7402
55
P7402 P59001
< RGB CPSV >