51
9.9.
DDR3_CH1 Section Schematic Diagram(2/2)
F
E
D
9
C
B
A
17
16
15
14
13
12
11
10
J3
BA2
K8
BA1
J2
BA0
N3
A13
K7
A12(/BC)
M7
A11
H7
A10(AP)
M3
A9
N8
A8
M2
A7
M8
A6
L2
A5
L8
A4
K2
A3
L3
A2
L7
A1
K3
A0
E7
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
D2
E8
E3
C8
C2
C7
B3
D3
/DQS
DQS
/CS
C3
H2
/RAS
/CAS
F3
/WE
G3
CKE
H3
CK
G9
F7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
M9
K9
D7
A9
A2
G2
G8
K1
M1
VDDQ
VDDQ
VDDQ
VDDQ
C1
B9
E2
E9
N7
A3
F1
F9
H1
NC
NC
NC
NC
NC
NC
NC
J7
H9
E1
J8
L9
N9
N1
VREFDQ
J9
VREFCA
L1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
J1
F8
F2
D8
A8
A1
B1
B2
B8
C9
D1
D9
/CK
DM/TDQS
G7
ODT
B7
ZQ
G1
H8
/RESET
N2
NU/(/TDQS)
A7
C1BA2
C1BA1
C1BA0
C1A13
C1A12
C1A11
C1A10
C1A9
C1A8
C1A7
C1A6
C1A5
C1A4
C1A3
C1A2
C1A1
C1A0
C1DQ19
C1DQ22
C1DQ21
C1DQ20
C1DQ23
C1DQ16
C1DQ17
C1DQ18
C1XDS1
C1DS2
C1XCS1
C1XRAS
C1XCAS
C1XWE
C1XRESET
C1CKE
C1CK
C1XCK
C1DM2
C1ODT
C52256
1
C52255
10
C52267
10
C52257
1
C52258
1
C52259
1
C52260
1
C52261
1
C52262
0.1
C52263
0.1
C52264
0.1
C52265
0.1
C52266
0.1
RL52234
RL52235
RL52236
RL52237
RL52238
RL52239
RL52240
RL52241
RL52242
RL52243
RL52288
RL52289
C52253
0.1
C52293
0.1
IC52203
C3ABTC000002
RL52211
RL52212
RL52213
RL52201
RL52202
RL52203
RL52204
RL52206
RL52207
RL52205
RL52208
RL52214
RL52215
RL52209
RL52210
R52221
240
DDR3 CH1(#2)
J3
BA2
K8
BA1
J2
BA0
N3
A13
K7
A12(/BC)
M7
A11
H7
A10(AP)
M3
A9
N8
A8
M2
A7
M8
A6
L2
A5
L8
A4
K2
A3
L3
A2
L7
A1
K3
A0
E7
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
D2
E8
E3
C8
C2
C7
B3
D3
/DQS
DQS
/CS
C3
H2
/RAS
/CAS
F3
/WE
G3
CKE
H3
CK
G9
F7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
M9
K9
D7
A9
A2
G2
G8
K1
M1
VDDQ
VDDQ
VDDQ
VDDQ
C1
B9
E2
E9
N7
A3
F1
F9
H1
NC
NC
NC
NC
NC
NC
NC
J7
H9
E1
J8
L9
N9
N1
VREFDQ
J9
VREFCA
L1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
J1
F8
F2
D8
A8
A1
B1
B2
B8
C9
D1
D9
/CK
DM/TDQS
G7
ODT
B7
ZQ
G1
H8
/RESET
N2
NU/(/TDQS)
A7
C1BA2
C1BA1
C1BA0
C1A13
C1A12
C1A11
C1A10
C1A9
C1A8
C1A7
C1A6
C1A5
C1A4
C1A3
C1A2
C1A1
C1A0
C1DQ27
C1DQ30
C1DQ25
C1DQ28
C1DQ31
C1DQ26
C1DQ29
C1DQ24
C1XDS3
C1DS3
C1XCS1
C1XRAS
C1XCAS
C1XWE
C1XRESET
C1CKE
C1CK
C1XCK
C1DM3
C1ODT
C52272
1
C52271
10
C52283
10
C52273
1
C52274
1
C52275
1
C52276
1
C52277
1
C52278
0.1
C52279
0.1
C52280
0.1
C52281
0.1
C52282
0.1
RL52280
RL52281
RL52282
RL52283
RL52284
RL52285
RL52286
RL52287
C52269
0.1
C52296
0.1
IC52204
C3ABTC000002
RL52256
RL52257
RL52258
RL52244
RL52245
RL52246
RL52247
RL52248
RL52250
RL52249
RL52251
RL52254
RL52255
RL52252
RL52253
R52224
240
DDR3 CH1(#0)
1
2
3
4
5
6
8
7
6
5
1
2
3
4
VTT
VLDOIN
VIN
VDDQSNS
VTREF
R52231
10K
C52289
1000P
C52290
10
C52286
10
C52291
1
C52285
10
C52288
10
C52292
1
C52287
1
VTSNS
S3
GND
PW_ST_D3.3V
DN
IC52205
C1ZBZ0004196
R52217
0
R52227
0
DMP-BDT300GA/GC/GN/PU
DDR3_CH1 SECTION(2/2)
SCHEMATIC DIAGRAM
(DIGITAL P.C.B(5/12))
LB52208
0
PW_PK_D1.5V_CO