5
4
Technical Descriptions
4.1.
Terminals Description
4.1.1.
Main Block
IC601:LC723781XX02
Note 1 :
Voltage measuerments are with respect to ground,
with a voltmeter (internal resistance : 10M
Ω
).
4.1.2.
Display Block
IC901:C0HBA0000225
PIN
No.
Port
Description
I/O
FM
(V)
AM
(V)
WB
(V)
1
XIN
Main system clock signal
input.
I
2.53
2.53
2.54
2
TEST2
Test terminal 2.
I
0
0
0
3
VREG
Regulator output bypass
condensor connected.
O
3
3
3
4
VSSCPU
GND
--
0
0
0
5
N.C.
Not connection.
O
0
0
0
6
N.C.
Not connection.
O
0
0
0
7
N.C.
Not connection.
O
0
0
0
8
N.C.
Not connection.
O
0
0
0
9
LCD_DO
LCD data signal output.
I
5.17
5.17
5.17
10
LCD_DI
LCD data signal input.
O
0
0
0
11
LCD_CLK
LCD clock signal output.
O
5.13
5.16
5.16
12
LCD_CE
LCD chip enable signal out-
put.
O
0
0
0
13
N.C.
Not connection.
O
0
0
0
14
N.C.
Not connection.
O
0
0
0
15
PDM_SCK
Radio preset direct memory
EEPROM I2C clock signal
output.
O
5.16
5.17
5.15
16
PDM_SDA
Radio preset direct memory
EEPROM I2C data signal
input.
I/O
5.15
5.16
5.17
17
N.C.
Not connection.
O
0
0
0
18
N.C.
Not connection.
O
0
0
0
19
N.C.
Not connection.
O
0
0
0
20
N.C.
Not connection.
O
0
0
0
21
N.C.
Not connection.
O
0
0
0
22
N.C.
Not connection.
O
0
0
0
23
N.C.
Not connection.
O
0
0
0
24
N.C.
Not connection.
O
0
0
0
25
N.C.
Not connection.
O
0
0
0
26
N.C.
Not connection.
O
0
0
0
27
N.C.
Not connection.
O
0
0
0
28
N.C.
Not connection.
O
0
0
0
29
N.C.
Not connection.
I
0
0
0
30
N.C.
Not connection.
I
0
0
0
31
N.C.
Not connection.
I
0
0
0
32
N.C.
Not connection.
I
0
0
0
33
N.C.
Not connection.
O
0
0
0
34
N.C.
Not connection.
O
0
0
0
35
N.C.
Not connection.
O
0
0
0
36
N.C.
Not connection.
O
0
0
0
37
N.C.
Not connection.
O
0
0
0
38
N.C.
Not connection.
O
0
0
0
39
VDDPORT
VDD +5V
-
5.16
5.16
5.16
40
VSSPORT
GND
-
0
0
0
41
N.C.
Not connection.
O
0
0
0
42
N.C.
Not connection.
O
0
0
0
43
N.C.
Not connection.
O
0
0
0
44
N.C.
Not connection.
O
0
0
0
45
N.C.
Not connection.
O
0
0
0
46
N.C.
Not connection.
O
0
0
0
47
N.C.
Not connection.
O
0
0
0
48
N.C.
Not connection.
O
0
0
0
49
PWR_CNT
Power-on control signal
output.
O
5.15
5.15
5.15
50
AMP_STB
Amp stby control signal out-
put.
O
5.15
5.15
5.15
51
AMP_MUT
E
Amp mute control signal.
O
0
0
0
52
N.C.
Not connection.
O
0
0
0
53
SSC
Tuner search sensitivity
change.
O
5.15
5.15
5.15
54
AF_MUTE
AF mute control signal out-
put(Pre-out).
O
0
0
0
55
E-
VOL_I2C_S
DA
Electronic Vol-IC data con-
trol signal.
I/O
5.16
5.16
5.15
56
E-
VOL_I2C_S
CK
Electronic Vol-IC clock con-
trol signal.
O
5.16
5.16
5.15
57
ILL_CNT
ILLM PWM control signal
input.
I
0.3
0.3
0.3
58
POWER_L
ED
Power LED signal control.
O
0.17
0.15
0.15
59
ILL_PWM
ILLM PWM control signal
output.
O
0.3
0.3
0.3
60
N.C.
Not connection.
O
0
0
0
61
ILL_P_SEN
S
Backlight ILLM on/off con-
trol signal detection input.
I
5.21
5.21
5.21
62
N.C.
Not connection.
O
0
0
0
63
N.C.
Not connection.
O
0
0
0
64
N.C.
Not connection.
O
0
0
0
65
N.C.
Not connection.
O
0
0
0
66
N.C.
Not connection.
O
0
0
0
67
BATT
Battery power connected
signal detection.
I
5.17
5.17
5.17
68
MODE_B
Rotary clock signal B out-
put.
I
5.13
5.13
5.13
69
N.C.
Not connection.
O
0
0
0
70
N.C.
Not connection.
O
0
0
0
71
MODE_A
Rotary clock signal A out-
put
I
5.13
5.13
5.13
72
N.C.
Not connection.
O
0
0
0
73
WB_MODE Wbpower control signal
output.
O
8
8
0
74
N.C.
Not connection.
O
0
0
0
75
RADIO_MO
DE
Radio power control signal
output.
O
0
0
8.35
76
FM/AM SW FM/AM control signal out-
put.
O
0
8
0
77
N.C.
Not connection.
I
0
0
0
78
ST_SW
Steering sw A/D control sig-
nal input.
I
0
0
0
79
BATT_LEV
EL
Battery voltage level detec-
tion signal input.
I
4.04
4.04
4.04
80
N.C.
Not connection.
I
0
0
0
81
VSSADC
GND
--
0
0
0
82
N.C.
Not connection.
I
0
0
0
83
ST
FM stereo signal input
I
5.23
5.23
1.48
84
VSM
FM/AM SD signal input.
I
0
0.5
0
85
N.C.
Not connection.
I
0
0
0
86
RESET
Reset signal input
I
5.17
5.17
5.17
87
ACC
ACC power connected sig-
nal detection
I
5.3
5.3
5.3
88
N.C.
Not connection.
I
0
0
0
89
N.C.
Not connection.
I
0
0
0
90
FM/AM_IFC FM/AM IFC signal input
I
0
0
0
91
N.C.
Not connection.
I
0
0
0
92
SUBPD
None
O
1.5
1.47
0
93
VDDPLL
Power supply of PLL
-
5.17
5.17
5.17
94
WB OSC
WB local oscillator signal
input.
I
0
0
1.49
95
OSC_FM/
AM
FM/AM OSC signal input
I
1.49
1.49
0
96
VSSPLL
GND
-
0
0
0
97
N.C.
Not connection.
O
0
0
0
98
EO1
PLL phase comparison
error output
O
1.47
1.45
1.38
99
TEST1
Test terminal 1.
-
0
0
0
100
XOUT
Main system clock crystal
connection.
O
2.62
2.62
2.62
PIN
No.
Port
Description
I/O
FM
(V)
AM
(V)
WB
(V)
crw405u.book Page 5 Thursday, January 14, 2010 2:17 PM