Panasonic AJSD955B - DVCPRO50 STUDIO DECK, Service Manual, Page: 211 / 562

F2B: A PROC BLOCK DIAGRAM
BLK-4
P4001 P100
P4001 P3000
P4001 P3002
P4002
F
rom A
V_J
A
CK
13C AES12_IN
55
131
203
103
IC4651<12>
43
131
50 130
NCE
CONF_DONE
30
91 92
194
195
45
46
193
P4001
T
o A
UDIO
P4002
P4001 P4002
P4001 P3002
P4001 P3000
P4001 P3000
P4001 P100
P4001 P100
P4001 P3002
P4001 P4002
P4001 P4002
196
LINE OUT 12
F16M OUT
F16M OUT
SRC2 OUT
173
132,133
31
83
171
SRC1 OUT
LINE OUT 34
FS JOG 12
FS JOG 34
MONIOUT
CUE MIX REC
CH1/CH2
CH3/CH4
130
127
126
129
128
RecInDatA CueOutDat
RECOutDatA
RecInDatB
RecInDatE
RecInDatF
RecInDatC
RecInDatD
IC4500<9>
IC4601<11>
56
57
58
AES
Decoder
122
84
83
82
81
77
39
14A AES34_IN
16B S REC_AUD 12
16C
15A
15B
9B
9C
24A
S REC_AUD 34
24A 24A DASD LR
26B 26B CUE_MIX_DATA
21A REC_DATA_12
21B
17B
17C
REC_DATA_34
23B DASD_12
23B
23B
23C
DASD_34
19C FS256
25C
16A
25C MCK1
15B S_PB_AUD12
15C S_PB_AUD34
14B AES12 OUT
14C
10B
10C
16A
16B AES34 OUT
204
4
197
49
DIGITAL IN 12
DIGITAL IN 34
E. E
A
CNT_PBIN_12
A
CNT_PBIN_34
P4001
P3002 P4001
P1
P4001
P4001
P4001
P4001
IC4400<7>
24C ADSD 12
198
200
202
24B ADSD 34
26A
24C
24B
26A
CUE_MET DATA
17A PB FS 1
18A PB FS 2
19A PB FS 256
PB FS 1
IN_BUFF
PB FS 2
PB FS 256
41
44
94
ANALOG IN 12
ANALOG IN 34
96
90
34
40
SER IN A
SER IN B SER OUT A
SER OUT B
FSA
FSB
17B PB DATA 12
18B PB DATA 34
34
35
11
12
13
14
17C PB FRM A1
7
8
142
5
6
2-9
2-9
2-4
6
8
5
7
4
6
8
18
1
13
25
32
28 16
2,7,31
14
12
2
19
14
12
14
15
18C PB FRM A2
28C A PROC_CLK18
22A A PROC_FEND
AV_IOWR_L
AV_RST_L
AV_IORD_L
AV_CS_APROC_L
11A ISP_TDI
11B ISP_TMS
12A 28A ISP_SEL2
11C ISP_TCK
12B ISP_TDO
20C
6B
6C
6A
2A 20C
5C
2B
13B
14B
15B
13C
14C
14A
15A
18A
18B
17A
A PROC_CLK27
AV_ADRS[0-10]
6
131
FS16M
48KHz_H
48KHz_H
SRAM
SLOW
F16M OUT
22C REF_CLK27_AP
DIF CNT 1/2
APC-LSI
AES
Decoder
PLL
Phase
CONV
Phase
CONV
Att
-6dB
Delay
REC
Volume
B/C
INT_SG
PCM_CTL 2/2
PBVolSel
MonSel
PBSel
REC
Delay
PB
Delay
Mute
delay
LPF
(3KHz)
Phase
CONV
PB
Volume
Meter
REC
SEL
Att
-6dB
IC4400<7>
179
104
NCEO
187
27
185
132,133
58
65
66
104
103 PBInDatA
PBInDatB
98
CueInDatA
Moni
Volume
RECOutDatB
PBOutDatA
PBOutDatB
ITS Delay
DV_PB_L
FPGA (PLD)
FPGA (PLD)
FPGA (PLD)
FPGA (PLD)
IC4100<3>
IN_BUFF
IC4101<3>
P4350
P4001
BUFF
IC4102<3>
BUFF
IC4350<6>
ROM for FPGA
IP4351<6>
IC4301<5>
FS256
IC4552<7>
IC4550,4551
4553,4554
IC4602<11>
TDO
TDI
TMS
TCK
SRAM 4
AV_DATA[0-7]
CLK
Converter
(CLK27 FS256)
CONF DONE
:ON L
LPF_EN_H_CH1
LPF_EN_H_CH2
LPF_EN_H_CH3
LPF_EN_H_CH4
CH1/CH2
CH3/CH4
67
68
FS_V
AUD_4CH_H
DV_PB_L
DV_PB_L
Phase
CONV
FS
ReGen
ITS Delay
SRC
Phase
CONV
Phase
CONV
Delay
Delay
Delay
Delay
Delay
Delay
AUD_4CH_H
AUD_4CH_H
DV_PB_L
IC4652<12>
43
46
47
48
49
30
42
42
SRC
H Other than above
L REF IN + STD
L PB
35
36
PB FS 256
PB FS 1
PB FS 2
AES ENCODER
AES ENCODER
AES ENCODER
AES ENCODER
Block Sync Gen.
DIFCNT
IC4500 <9>
2/2
PCMCTL 1/2
A
V_D
A
T
A & A
V_ADRS etc
AV_DATA & AV_ADRS etc
DATA & CLK
DATA & CLK
F
rom SDI
F
rom
V_OUT
F
rom
SYSCON
P100 P4001
F
rom
A
V_J
A
CK
F
rom /
T
o
F
rom A
UDIO
F
rom REC_PB
F
rom A
UDIO
,V_IN,
SDI,SDTI,REC_PB
,
V_OUT
,SYSCON
T
o/F
rom A
UDIO
,
V_IN,SDI,SDTI,
REC_PB
,V_OUT
,
SYSCON
PLD
Wr
iter
Via Rear J
ac
k
9B
7A
T
o
A
UDIO
T
o
REC_PB
T
o
A
UDIO
T
o
REC_PB
T
o SDI
T
o A
V_J
A
CK
<<REC & EE Signal>> <<PLAYBACK Signal>> <<Original>>
12C CONF_INFO
T
o
SYSCON